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[people/ms/u-boot.git] / board / amcc / yucca / yucca.c
1 /*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * Port to AMCC-440SPE Evaluation Board SOP - April 2005
24 *
25 * PCIe supporting routines derived from Linux 440SPe PCIe driver.
26 */
27
28 #include <common.h>
29 #include <ppc4xx.h>
30 #include <i2c.h>
31 #include <asm/processor.h>
32 #include <asm/io.h>
33 #include <asm/4xx_pcie.h>
34
35 #include "yucca.h"
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 void fpga_init (void);
40
41 #define DEBUG_ENV
42 #ifdef DEBUG_ENV
43 #define DEBUGF(fmt,args...) printf(fmt ,##args)
44 #else
45 #define DEBUGF(fmt,args...)
46 #endif
47
48 #define FALSE 0
49 #define TRUE 1
50
51 int board_early_init_f (void)
52 {
53 /*----------------------------------------------------------------------------+
54 | Define Boot devices
55 +----------------------------------------------------------------------------*/
56 #define BOOT_FROM_SMALL_FLASH 0x00
57 #define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01
58 #define BOOT_FROM_PCI 0x02
59 #define BOOT_DEVICE_UNKNOWN 0x03
60
61 /*----------------------------------------------------------------------------+
62 | EBC Devices Characteristics
63 | Peripheral Bank Access Parameters - EBC_BxAP
64 | Peripheral Bank Configuration Register - EBC_BxCR
65 +----------------------------------------------------------------------------*/
66
67 /*
68 * Small Flash and FRAM
69 * BU Value
70 * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
71 * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
72 * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
73 */
74 #define EBC_BXAP_SMALL_FLASH EBC_BXAP_BME_DISABLED | \
75 EBC_BXAP_TWT_ENCODE(7) | \
76 EBC_BXAP_BCE_DISABLE | \
77 EBC_BXAP_BCT_2TRANS | \
78 EBC_BXAP_CSN_ENCODE(0) | \
79 EBC_BXAP_OEN_ENCODE(0) | \
80 EBC_BXAP_WBN_ENCODE(0) | \
81 EBC_BXAP_WBF_ENCODE(0) | \
82 EBC_BXAP_TH_ENCODE(0) | \
83 EBC_BXAP_RE_DISABLED | \
84 EBC_BXAP_SOR_DELAYED | \
85 EBC_BXAP_BEM_WRITEONLY | \
86 EBC_BXAP_PEN_DISABLED
87
88 #define EBC_BXCR_SMALL_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
89 EBC_BXCR_BS_16MB | \
90 EBC_BXCR_BU_RW | \
91 EBC_BXCR_BW_8BIT
92
93 #define EBC_BXCR_SMALL_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xe7000000) | \
94 EBC_BXCR_BS_16MB | \
95 EBC_BXCR_BU_RW | \
96 EBC_BXCR_BW_8BIT
97
98 /*
99 * Large Flash and SRAM
100 * BU Value
101 * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
102 * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
103 * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
104 */
105 #define EBC_BXAP_LARGE_FLASH EBC_BXAP_BME_DISABLED | \
106 EBC_BXAP_TWT_ENCODE(7) | \
107 EBC_BXAP_BCE_DISABLE | \
108 EBC_BXAP_BCT_2TRANS | \
109 EBC_BXAP_CSN_ENCODE(0) | \
110 EBC_BXAP_OEN_ENCODE(0) | \
111 EBC_BXAP_WBN_ENCODE(0) | \
112 EBC_BXAP_WBF_ENCODE(0) | \
113 EBC_BXAP_TH_ENCODE(0) | \
114 EBC_BXAP_RE_DISABLED | \
115 EBC_BXAP_SOR_DELAYED | \
116 EBC_BXAP_BEM_WRITEONLY | \
117 EBC_BXAP_PEN_DISABLED
118
119 #define EBC_BXCR_LARGE_FLASH_CS0 EBC_BXCR_BAS_ENCODE(0xFF000000) | \
120 EBC_BXCR_BS_16MB | \
121 EBC_BXCR_BU_RW | \
122 EBC_BXCR_BW_16BIT
123
124 #define EBC_BXCR_LARGE_FLASH_CS2 EBC_BXCR_BAS_ENCODE(0xE7000000) | \
125 EBC_BXCR_BS_16MB | \
126 EBC_BXCR_BU_RW | \
127 EBC_BXCR_BW_16BIT
128
129 /*
130 * FPGA
131 * BU value :
132 * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
133 * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
134 */
135 #define EBC_BXAP_FPGA EBC_BXAP_BME_DISABLED | \
136 EBC_BXAP_TWT_ENCODE(11) | \
137 EBC_BXAP_BCE_DISABLE | \
138 EBC_BXAP_BCT_2TRANS | \
139 EBC_BXAP_CSN_ENCODE(10) | \
140 EBC_BXAP_OEN_ENCODE(1) | \
141 EBC_BXAP_WBN_ENCODE(1) | \
142 EBC_BXAP_WBF_ENCODE(1) | \
143 EBC_BXAP_TH_ENCODE(1) | \
144 EBC_BXAP_RE_DISABLED | \
145 EBC_BXAP_SOR_DELAYED | \
146 EBC_BXAP_BEM_RW | \
147 EBC_BXAP_PEN_DISABLED
148
149 #define EBC_BXCR_FPGA_CS1 EBC_BXCR_BAS_ENCODE(0xe2000000) | \
150 EBC_BXCR_BS_1MB | \
151 EBC_BXCR_BU_RW | \
152 EBC_BXCR_BW_16BIT
153
154 unsigned long mfr;
155 /*
156 * Define Variables for EBC initialization depending on BOOTSTRAP option
157 */
158 unsigned long sdr0_pinstp, sdr0_sdstp1 ;
159 unsigned long bootstrap_settings, ebc_data_width, boot_selection;
160 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
161
162 /*-------------------------------------------------------------------+
163 | Initialize EBC CONFIG -
164 | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
165 | default value :
166 | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
167 |
168 +-------------------------------------------------------------------*/
169 mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
170 EBC_CFG_PTD_ENABLE |
171 EBC_CFG_RTC_16PERCLK |
172 EBC_CFG_ATC_PREVIOUS |
173 EBC_CFG_DTC_PREVIOUS |
174 EBC_CFG_CTC_PREVIOUS |
175 EBC_CFG_OEO_PREVIOUS |
176 EBC_CFG_EMC_DEFAULT |
177 EBC_CFG_PME_DISABLE |
178 EBC_CFG_PR_16);
179
180 /*-------------------------------------------------------------------+
181 |
182 | PART 1 : Initialize EBC Bank 1
183 | ==============================
184 | Bank1 is always associated to the EPLD.
185 | It has to be initialized prior to other banks settings computation
186 | since some board registers values may be needed to determine the
187 | boot type
188 |
189 +-------------------------------------------------------------------*/
190 mtebc(pb1ap, EBC_BXAP_FPGA);
191 mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
192
193 /*-------------------------------------------------------------------+
194 |
195 | PART 2 : Determine which boot device was selected
196 | =================================================
197 |
198 | Read Pin Strap Register in PPC440SPe
199 | Result can either be :
200 | - Boot strap = boot from EBC 8bits => Small Flash
201 | - Boot strap = boot from PCI
202 | - Boot strap = IIC
203 | In case of boot from IIC, read Serial Device Strap Register1
204 |
205 | Result can either be :
206 | - Boot from EBC - EBC Bus Width = 8bits => Small Flash
207 | - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
208 | - Boot from PCI
209 |
210 +-------------------------------------------------------------------*/
211 /* Read Pin Strap Register in PPC440SP */
212 mfsdr(SDR0_PINSTP, sdr0_pinstp);
213 bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
214
215 switch (bootstrap_settings) {
216 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
217 /*
218 * Strapping Option A
219 * Boot from EBC - 8 bits , Small Flash
220 */
221 computed_boot_device = BOOT_FROM_SMALL_FLASH;
222 break;
223 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
224 /*
225 * Strappping Option B
226 * Boot from PCI
227 */
228 computed_boot_device = BOOT_FROM_PCI;
229 break;
230 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
231 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
232 /*
233 * Strapping Option C or D
234 * Boot Settings in IIC EEprom address 0x50 or 0x54
235 * Read Serial Device Strap Register1 in PPC440SPe
236 */
237 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
238 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
239 ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
240
241 switch (boot_selection) {
242 case SDR0_SDSTP1_ERPN_EBC:
243 switch (ebc_data_width) {
244 case SDR0_SDSTP1_EBCW_16_BITS:
245 computed_boot_device =
246 BOOT_FROM_LARGE_FLASH_OR_SRAM;
247 break;
248 case SDR0_SDSTP1_EBCW_8_BITS :
249 computed_boot_device = BOOT_FROM_SMALL_FLASH;
250 break;
251 }
252 break;
253
254 case SDR0_SDSTP1_ERPN_PCI:
255 computed_boot_device = BOOT_FROM_PCI;
256 break;
257 default:
258 /* should not occure */
259 computed_boot_device = BOOT_DEVICE_UNKNOWN;
260 }
261 break;
262 default:
263 /* should not be */
264 computed_boot_device = BOOT_DEVICE_UNKNOWN;
265 break;
266 }
267
268 /*-------------------------------------------------------------------+
269 |
270 | PART 3 : Compute EBC settings depending on selected boot device
271 | ====== ======================================================
272 |
273 | Resulting EBC init will be among following configurations :
274 |
275 | - Boot from EBC 8bits => boot from Small Flash selected
276 | EBC-CS0 = Small Flash
277 | EBC-CS2 = Large Flash and SRAM
278 |
279 | - Boot from EBC 16bits => boot from Large Flash or SRAM
280 | EBC-CS0 = Large Flash or SRAM
281 | EBC-CS2 = Small Flash
282 |
283 | - Boot from PCI
284 | EBC-CS0 = not initialized to avoid address contention
285 | EBC-CS2 = same as boot from Small Flash selected
286 |
287 +-------------------------------------------------------------------*/
288 unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
289 unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
290
291 switch (computed_boot_device) {
292 /*-------------------------------------------------------------------*/
293 case BOOT_FROM_PCI:
294 /*-------------------------------------------------------------------*/
295 /*
296 * By Default CS2 is affected to LARGE Flash
297 * do not initialize SMALL FLASH to avoid address contention
298 * Large Flash
299 */
300 ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
301 ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
302 break;
303
304 /*-------------------------------------------------------------------*/
305 case BOOT_FROM_SMALL_FLASH:
306 /*-------------------------------------------------------------------*/
307 ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
308 ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
309
310 /*
311 * Large Flash or SRAM
312 */
313 /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
314 ebc0_cs2_bxap_value = 0x048ff240;
315 ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
316 break;
317
318 /*-------------------------------------------------------------------*/
319 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
320 /*-------------------------------------------------------------------*/
321 ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
322 ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
323
324 /* Small flash */
325 ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
326 ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
327 break;
328
329 /*-------------------------------------------------------------------*/
330 default:
331 /*-------------------------------------------------------------------*/
332 /* BOOT_DEVICE_UNKNOWN */
333 break;
334 }
335
336 mtebc(pb0ap, ebc0_cs0_bxap_value);
337 mtebc(pb0cr, ebc0_cs0_bxcr_value);
338 mtebc(pb2ap, ebc0_cs2_bxap_value);
339 mtebc(pb2cr, ebc0_cs2_bxcr_value);
340
341 /*--------------------------------------------------------------------+
342 | Interrupt controller setup for the AMCC 440SPe Evaluation board.
343 +--------------------------------------------------------------------+
344 +---------------------------------------------------------------------+
345 |Interrupt| Source | Pol. | Sensi.| Crit. |
346 +---------+-----------------------------------+-------+-------+-------+
347 | IRQ 00 | UART0 | High | Level | Non |
348 | IRQ 01 | UART1 | High | Level | Non |
349 | IRQ 02 | IIC0 | High | Level | Non |
350 | IRQ 03 | IIC1 | High | Level | Non |
351 | IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
352 | IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
353 | IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
354 | IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
355 | IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
356 | IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
357 | IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
358 | IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
359 | IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
360 | IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
361 | IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
362 | IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
363 | IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
364 | IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
365 | IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
366 | IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
367 | IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
368 | IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
369 | IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
370 | IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
371 | IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
372 | IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
373 | IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
374 | IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
375 | IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
376 | IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
377 | IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
378 | IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
379 |----------------------------------------------------------------------
380 | IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
381 | IRQ 33 | MAL Serr | High | Level | Non |
382 | IRQ 34 | MAL Txde | High | Level | Non |
383 | IRQ 35 | MAL Rxde | High | Level | Non |
384 | IRQ 36 | DMC CE or DMC UE | High | Level | Non |
385 | IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
386 | IRQ 38 | MAL TX EOB | High | Level | Non |
387 | IRQ 39 | MAL RX EOB | High | Level | Non |
388 | IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
389 | IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
390 | IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
391 | IRQ 43 | L2 Cache | Risin | Edge | Non |
392 | IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
393 | IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
394 | IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
395 | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
396 | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
397 | IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
398 | IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
399 | IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
400 | IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
401 | IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
402 | IRQ 54 | DMA Error | High | Level | Non |
403 | IRQ 55 | DMA I2O Error | High | Level | Non |
404 | IRQ 56 | Serial ROM | High | Level | Non |
405 | IRQ 57 | PCIX0 Error | High | Edge | Non |
406 | IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
407 | IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
408 | IRQ 60 | EMAC0 Interrupt | High | Level | Non |
409 | IRQ 61 | EMAC0 Wake-up | High | Level | Non |
410 | IRQ 62 | Reserved | High | Level | Non |
411 | IRQ 63 | XOR | High | Level | Non |
412 |----------------------------------------------------------------------
413 | IRQ 64 | PE0 AL | High | Level | Non |
414 | IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
415 | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
416 | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
417 | IRQ 68 | PE0 TCR | High | Level | Non |
418 | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
419 | IRQ 70 | PE0 DCR Error | High | Level | Non |
420 | IRQ 71 | Reserved | N/A | N/A | Non |
421 | IRQ 72 | PE1 AL | High | Level | Non |
422 | IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
423 | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
424 | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
425 | IRQ 76 | PE1 TCR | High | Level | Non |
426 | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
427 | IRQ 78 | PE1 DCR Error | High | Level | Non |
428 | IRQ 79 | Reserved | N/A | N/A | Non |
429 | IRQ 80 | PE2 AL | High | Level | Non |
430 | IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
431 | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
432 | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
433 | IRQ 84 | PE2 TCR | High | Level | Non |
434 | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
435 | IRQ 86 | PE2 DCR Error | High | Level | Non |
436 | IRQ 87 | Reserved | N/A | N/A | Non |
437 | IRQ 88 | External IRQ(5) | Progr | Progr | Non |
438 | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
439 | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
440 | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
441 | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
442 | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
443 | IRQ 94 | Reserved | N/A | N/A | Non |
444 | IRQ 95 | Reserved | N/A | N/A | Non |
445 |---------------------------------------------------------------------
446 | IRQ 96 | PE0 INTA | High | Level | Non |
447 | IRQ 97 | PE0 INTB | High | Level | Non |
448 | IRQ 98 | PE0 INTC | High | Level | Non |
449 | IRQ 99 | PE0 INTD | High | Level | Non |
450 | IRQ 100 | PE1 INTA | High | Level | Non |
451 | IRQ 101 | PE1 INTB | High | Level | Non |
452 | IRQ 102 | PE1 INTC | High | Level | Non |
453 | IRQ 103 | PE1 INTD | High | Level | Non |
454 | IRQ 104 | PE2 INTA | High | Level | Non |
455 | IRQ 105 | PE2 INTB | High | Level | Non |
456 | IRQ 106 | PE2 INTC | High | Level | Non |
457 | IRQ 107 | PE2 INTD | Risin | Edge | Non |
458 | IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
459 | IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
460 | IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
461 | IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
462 | IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
463 | IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
464 | IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
465 | IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
466 | IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
467 | IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
468 | IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
469 | IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
470 | IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
471 | IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
472 | IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
473 | IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
474 | IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
475 | IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
476 | IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
477 | IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
478 +---------+-----------------------------------+-------+-------+------*/
479 /*--------------------------------------------------------------------+
480 | Put UICs in PowerPC440SPemode.
481 | Initialise UIC registers. Clear all interrupts. Disable all
482 | interrupts.
483 | Set critical interrupt values. Set interrupt polarities. Set
484 | interrupt trigger levels. Make bit 0 High priority. Clear all
485 | interrupts again.
486 +-------------------------------------------------------------------*/
487 mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
488 mtdcr (uic3er, 0x00000000); /* disable all interrupts */
489 mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical
490 * interrupts */
491 mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities */
492 mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
493 mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest
494 * priority */
495 mtdcr (uic3sr, 0x00000000); /* clear all interrupts */
496 mtdcr (uic3sr, 0xffffffff); /* clear all interrupts */
497
498 mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
499 mtdcr (uic2er, 0x00000000); /* disable all interrupts */
500 mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical
501 * interrupts */
502 mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities */
503 mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
504 mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest
505 * priority */
506 mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
507 mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
508
509 mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
510 mtdcr (uic1er, 0x00000000); /* disable all interrupts */
511 mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical
512 * interrupts */
513 mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
514 mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels */
515 mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest
516 * priority */
517 mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
518 mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
519
520 mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
521 mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted
522 * cascade to be checked */
523 mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical
524 * interrupts */
525 mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities */
526 mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
527 mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest
528 * priority */
529 mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
530 mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
531
532 mfsdr(sdr_mfr, mfr);
533 mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
534 mtsdr(sdr_mfr, mfr);
535
536 fpga_init();
537
538 return 0;
539 }
540
541 int checkboard (void)
542 {
543 char *s = getenv("serial#");
544
545 printf("Board: Yucca - AMCC 440SPe Evaluation Board");
546 if (s != NULL) {
547 puts(", serial# ");
548 puts(s);
549 }
550 putc('\n');
551
552 return 0;
553 }
554
555 /*
556 * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
557 * board specific values.
558 */
559 static int ppc440spe_rev_a(void)
560 {
561 if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
562 return 1;
563 else
564 return 0;
565 }
566
567 u32 ddr_wrdtr(u32 default_val) {
568 /*
569 * Yucca boards with 440SPe rev. A need a slightly different setup
570 * for the MCIF0_WRDTR register.
571 */
572 if (ppc440spe_rev_a())
573 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
574
575 return default_val;
576 }
577
578 u32 ddr_clktr(u32 default_val) {
579 /*
580 * Yucca boards with 440SPe rev. A need a slightly different setup
581 * for the MCIF0_CLKTR register.
582 */
583 if (ppc440spe_rev_a())
584 return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
585
586 return default_val;
587 }
588
589 #if defined(CFG_DRAM_TEST)
590 int testdram (void)
591 {
592 uint *pstart = (uint *) 0x00000000;
593 uint *pend = (uint *) 0x08000000;
594 uint *p;
595
596 for (p = pstart; p < pend; p++)
597 *p = 0xaaaaaaaa;
598
599 for (p = pstart; p < pend; p++) {
600 if (*p != 0xaaaaaaaa) {
601 printf ("SDRAM test fails at: %08x\n", (uint) p);
602 return 1;
603 }
604 }
605
606 for (p = pstart; p < pend; p++)
607 *p = 0x55555555;
608
609 for (p = pstart; p < pend; p++) {
610 if (*p != 0x55555555) {
611 printf ("SDRAM test fails at: %08x\n", (uint) p);
612 return 1;
613 }
614 }
615 return 0;
616 }
617 #endif
618
619 /*************************************************************************
620 * pci_pre_init
621 *
622 * This routine is called just prior to registering the hose and gives
623 * the board the opportunity to check things. Returning a value of zero
624 * indicates that things are bad & PCI initialization should be aborted.
625 *
626 * Different boards may wish to customize the pci controller structure
627 * (add regions, override default access routines, etc) or perform
628 * certain pre-initialization actions.
629 *
630 ************************************************************************/
631 #if defined(CONFIG_PCI)
632 int pci_pre_init(struct pci_controller * hose )
633 {
634 unsigned long strap;
635
636 /*-------------------------------------------------------------------+
637 * The yucca board is always configured as the host & requires the
638 * PCI arbiter to be enabled.
639 *-------------------------------------------------------------------*/
640 mfsdr(sdr_sdstp1, strap);
641 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
642 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
643 return 0;
644 }
645
646 return 1;
647 }
648 #endif /* defined(CONFIG_PCI) */
649
650 /*************************************************************************
651 * pci_target_init
652 *
653 * The bootstrap configuration provides default settings for the pci
654 * inbound map (PIM). But the bootstrap config choices are limited and
655 * may not be sufficient for a given board.
656 *
657 ************************************************************************/
658 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
659 void pci_target_init(struct pci_controller * hose )
660 {
661 /*-------------------------------------------------------------------+
662 * Disable everything
663 *-------------------------------------------------------------------*/
664 out32r( PCIX0_PIM0SA, 0 ); /* disable */
665 out32r( PCIX0_PIM1SA, 0 ); /* disable */
666 out32r( PCIX0_PIM2SA, 0 ); /* disable */
667 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
668
669 /*-------------------------------------------------------------------+
670 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
671 * strapping options to not support sizes such as 128/256 MB.
672 *-------------------------------------------------------------------*/
673 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
674 out32r( PCIX0_PIM0LAH, 0 );
675 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
676 out32r( PCIX0_BAR0, 0 );
677
678 /*-------------------------------------------------------------------+
679 * Program the board's subsystem id/vendor id
680 *-------------------------------------------------------------------*/
681 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
682 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
683
684 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
685 }
686 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
687
688 #if defined(CONFIG_PCI)
689 /*************************************************************************
690 * is_pci_host
691 *
692 * This routine is called to determine if a pci scan should be
693 * performed. With various hardware environments (especially cPCI and
694 * PPMC) it's insufficient to depend on the state of the arbiter enable
695 * bit in the strap register, or generic host/adapter assumptions.
696 *
697 * Rather than hard-code a bad assumption in the general 440 code, the
698 * 440 pci code requires the board to decide at runtime.
699 *
700 * Return 0 for adapter mode, non-zero for host (monarch) mode.
701 *
702 *
703 ************************************************************************/
704 int is_pci_host(struct pci_controller *hose)
705 {
706 /* The yucca board is always configured as host. */
707 return 1;
708 }
709
710 int yucca_pcie_card_present(int port)
711 {
712 u16 reg;
713
714 reg = in_be16((u16 *)FPGA_REG1C);
715 switch(port) {
716 case 0:
717 return !(reg & FPGA_REG1C_PE0_PRSNT);
718 case 1:
719 return !(reg & FPGA_REG1C_PE1_PRSNT);
720 case 2:
721 return !(reg & FPGA_REG1C_PE2_PRSNT);
722 default:
723 return 0;
724 }
725 }
726
727 /*
728 * For the given slot, set rootpoint mode, send power to the slot,
729 * turn on the green LED and turn off the yellow LED, enable the clock
730 * and turn off reset.
731 */
732 void yucca_setup_pcie_fpga_rootpoint(int port)
733 {
734 u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
735
736 switch(port) {
737 case 0:
738 rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
739 endpoint = 0;
740 power = FPGA_REG1A_PE0_PWRON;
741 green_led = FPGA_REG1A_PE0_GLED;
742 clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
743 yellow_led = FPGA_REG1A_PE0_YLED;
744 reset_off = FPGA_REG1C_PE0_PERST;
745 break;
746 case 1:
747 rootpoint = 0;
748 endpoint = FPGA_REG1C_PE1_ENDPOINT;
749 power = FPGA_REG1A_PE1_PWRON;
750 green_led = FPGA_REG1A_PE1_GLED;
751 clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
752 yellow_led = FPGA_REG1A_PE1_YLED;
753 reset_off = FPGA_REG1C_PE1_PERST;
754 break;
755 case 2:
756 rootpoint = 0;
757 endpoint = FPGA_REG1C_PE2_ENDPOINT;
758 power = FPGA_REG1A_PE2_PWRON;
759 green_led = FPGA_REG1A_PE2_GLED;
760 clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
761 yellow_led = FPGA_REG1A_PE2_YLED;
762 reset_off = FPGA_REG1C_PE2_PERST;
763 break;
764
765 default:
766 return;
767 }
768
769 out_be16((u16 *)FPGA_REG1A,
770 ~(power | clock | green_led) &
771 (yellow_led | in_be16((u16 *)FPGA_REG1A)));
772
773 out_be16((u16 *)FPGA_REG1C,
774 ~(endpoint | reset_off) &
775 (rootpoint | in_be16((u16 *)FPGA_REG1C)));
776 /*
777 * Leave device in reset for a while after powering on the
778 * slot to give it a chance to initialize.
779 */
780 udelay(250 * 1000);
781
782 out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
783 }
784 /*
785 * For the given slot, set endpoint mode, send power to the slot,
786 * turn on the green LED and turn off the yellow LED, enable the clock
787 * .In end point mode reset bit is read only.
788 */
789 void yucca_setup_pcie_fpga_endpoint(int port)
790 {
791 u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
792
793 switch(port) {
794 case 0:
795 rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
796 endpoint = 0;
797 power = FPGA_REG1A_PE0_PWRON;
798 green_led = FPGA_REG1A_PE0_GLED;
799 clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
800 yellow_led = FPGA_REG1A_PE0_YLED;
801 reset_off = FPGA_REG1C_PE0_PERST;
802 break;
803 case 1:
804 rootpoint = 0;
805 endpoint = FPGA_REG1C_PE1_ENDPOINT;
806 power = FPGA_REG1A_PE1_PWRON;
807 green_led = FPGA_REG1A_PE1_GLED;
808 clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
809 yellow_led = FPGA_REG1A_PE1_YLED;
810 reset_off = FPGA_REG1C_PE1_PERST;
811 break;
812 case 2:
813 rootpoint = 0;
814 endpoint = FPGA_REG1C_PE2_ENDPOINT;
815 power = FPGA_REG1A_PE2_PWRON;
816 green_led = FPGA_REG1A_PE2_GLED;
817 clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
818 yellow_led = FPGA_REG1A_PE2_YLED;
819 reset_off = FPGA_REG1C_PE2_PERST;
820 break;
821
822 default:
823 return;
824 }
825
826 out_be16((u16 *)FPGA_REG1A,
827 ~(power | clock | green_led) &
828 (yellow_led | in_be16((u16 *)FPGA_REG1A)));
829
830 out_be16((u16 *)FPGA_REG1C,
831 ~(rootpoint | reset_off) &
832 (endpoint | in_be16((u16 *)FPGA_REG1C)));
833 }
834
835 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
836
837 void pcie_setup_hoses(int busno)
838 {
839 struct pci_controller *hose;
840 int i, bus;
841 int ret = 0;
842 char *env;
843 unsigned int delay;
844
845 /*
846 * assume we're called after the PCIX hose is initialized, which takes
847 * bus ID 0 and therefore start numbering PCIe's from 1.
848 */
849 bus = busno;
850 for (i = 0; i <= 2; i++) {
851 /* Check for yucca card presence */
852 if (!yucca_pcie_card_present(i))
853 continue;
854
855 if (is_end_point(i)) {
856 yucca_setup_pcie_fpga_endpoint(i);
857 ret = ppc4xx_init_pcie_endport(i);
858 } else {
859 yucca_setup_pcie_fpga_rootpoint(i);
860 ret = ppc4xx_init_pcie_rootport(i);
861 }
862 if (ret) {
863 printf("PCIE%d: initialization as %s failed\n", i,
864 is_end_point(i) ? "endpoint" : "root-complex");
865 continue;
866 }
867
868 hose = &pcie_hose[i];
869 hose->first_busno = bus;
870 hose->last_busno = bus;
871 hose->current_busno = bus;
872
873 /* setup mem resource */
874 pci_set_region(hose->regions + 0,
875 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
876 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
877 CFG_PCIE_MEMSIZE,
878 PCI_REGION_MEM);
879 hose->region_count = 1;
880 pci_register_hose(hose);
881
882 if (is_end_point(i)) {
883 ppc4xx_setup_pcie_endpoint(hose, i);
884 /*
885 * Reson for no scanning is endpoint can not generate
886 * upstream configuration accesses.
887 */
888 } else {
889 ppc4xx_setup_pcie_rootpoint(hose, i);
890 env = getenv("pciscandelay");
891 if (env != NULL) {
892 delay = simple_strtoul(env, NULL, 10);
893 if (delay > 5)
894 printf("Warning, expect noticable delay before "
895 "PCIe scan due to 'pciscandelay' value!\n");
896 mdelay(delay * 1000);
897 }
898
899 /*
900 * Config access can only go down stream
901 */
902 hose->last_busno = pci_hose_scan(hose);
903 bus = hose->last_busno + 1;
904 }
905 }
906 }
907 #endif /* defined(CONFIG_PCI) */
908
909 int misc_init_f (void)
910 {
911 uint reg;
912 #if defined(CONFIG_STRESS)
913 uint i ;
914 uint disp;
915 #endif
916
917 out16(FPGA_REG10, (in16(FPGA_REG10) &
918 ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
919 FPGA_REG10_10MHZ_ENABLE |
920 FPGA_REG10_100MHZ_ENABLE |
921 FPGA_REG10_GIGABIT_ENABLE |
922 FPGA_REG10_FULL_DUPLEX );
923
924 udelay(10000); /* wait 10ms */
925
926 out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
927
928 /* minimal init for PCIe */
929 /* pci express 0 Endpoint Mode */
930 mfsdr(SDR0_PE0DLPSET, reg);
931 reg &= (~0x00400000);
932 mtsdr(SDR0_PE0DLPSET, reg);
933 /* pci express 1 Rootpoint Mode */
934 mfsdr(SDR0_PE1DLPSET, reg);
935 reg |= 0x00400000;
936 mtsdr(SDR0_PE1DLPSET, reg);
937 /* pci express 2 Rootpoint Mode */
938 mfsdr(SDR0_PE2DLPSET, reg);
939 reg |= 0x00400000;
940 mtsdr(SDR0_PE2DLPSET, reg);
941
942 out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
943 ~FPGA_REG1C_PE0_ROOTPOINT &
944 ~FPGA_REG1C_PE1_ENDPOINT &
945 ~FPGA_REG1C_PE2_ENDPOINT));
946
947 #if defined(CONFIG_STRESS)
948 /*
949 * all this setting done by linux only needed by stress an charac. test
950 * procedure
951 * PCIe 1 Rootpoint PCIe2 Endpoint
952 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
953 * Power Level
954 */
955 for (i = 0, disp = 0; i < 8; i++, disp += 3) {
956 mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
957 reg |= 0x33000000;
958 mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
959 }
960
961 /*
962 * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
963 * Power Level
964 */
965 for (i = 0, disp = 0; i < 4; i++, disp += 3) {
966 mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
967 reg |= 0x33000000;
968 mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
969 }
970
971 /*
972 * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
973 * Power Level
974 */
975 for (i = 0, disp = 0; i < 4; i++, disp += 3) {
976 mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
977 reg |= 0x33000000;
978 mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
979 }
980
981 reg = 0x21242222;
982 mtsdr(SDR0_PE2UTLSET1, reg);
983 reg = 0x11000000;
984 mtsdr(SDR0_PE2UTLSET2, reg);
985 /* pci express 1 Endpoint Mode */
986 reg = 0x00004000;
987 mtsdr(SDR0_PE2DLPSET, reg);
988
989 mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
990 #endif
991 return 0;
992 }
993
994 void fpga_init(void)
995 {
996 /*
997 * by default sdram access is disabled by fpga
998 */
999 out16(FPGA_REG10, (in16 (FPGA_REG10) |
1000 FPGA_REG10_SDRAM_ENABLE |
1001 FPGA_REG10_ENABLE_DISPLAY ));
1002
1003 return;
1004 }
1005
1006 #ifdef CONFIG_POST
1007 /*
1008 * Returns 1 if keys pressed to start the power-on long-running tests
1009 * Called from board_init_f().
1010 */
1011 int post_hotkeys_pressed(void)
1012 {
1013 return (ctrlc());
1014 }
1015 #endif
1016
1017 /*---------------------------------------------------------------------------+
1018 | onboard_pci_arbiter_selected => from EPLD
1019 +---------------------------------------------------------------------------*/
1020 int onboard_pci_arbiter_selected(int core_pci)
1021 {
1022 #if 0
1023 unsigned long onboard_pci_arbiter_sel;
1024
1025 onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
1026
1027 if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
1028 return (BOARD_OPTION_SELECTED);
1029 else
1030 #endif
1031 return (BOARD_OPTION_NOT_SELECTED);
1032 }
"Das U-Boot" Source Tree