board/apollon/mem.h

   1 /*
   2  * (C) Copyright 2005-2007
   3  * Samsung Electronics,
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef _APOLLON_OMAP24XX_MEM_H_
  26 #define _APOLLON_OMAP24XX_MEM_H_
  27
  28 /* Slower full frequency range default timings for x32 operation*/
  29 #define APOLLON_2420_SDRC_SHARING               0x00000100
  30 #define APOLLON_2420_SDRC_MDCFG_0_DDR           0x00d04011
  31 #define APOLLON_2420_SDRC_MR_0_DDR              0x00000032
  32
  33 /* optimized timings good for current shipping parts */
  34 #define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz  0x4A59B485
  35 #define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz  0x0000000C
  36
  37 #define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz  0x7BA35907
  38 #define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz  0x00000013
  39
  40 #define APOLLON_242X_SDRC_RFR_CTRL_100MHz       0x00030001
  41 #define APOLLON_242X_SDRC_RFR_CTRL_166MHz       0x00044C01
  42
  43 #define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz     0x00007306
  44 #define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz     0x00000506
  45
  46 #ifdef PRCM_CONFIG_I
  47 #define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
  48 #define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
  49 #define APOLLON_2420_SDRC_RFR_CTRL      APOLLON_242X_SDRC_RFR_CTRL_166MHz
  50 #define APOLLON_2420_SDRC_DLLAB_CTRL    APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
  51 #elif PRCM_CONFIG_II
  52 #define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
  53 #define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
  54 #define APOLLON_2420_SDRC_RFR_CTRL      APOLLON_242X_SDRC_RFR_CTRL_100MHz
  55 #define APOLLON_2420_SDRC_DLLAB_CTRL    APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
  56 #endif
  57
  58 /* GPMC settings */
  59 #ifdef PRCM_CONFIG_I            /* L3 at 165MHz */
  60 /* CS0: OneNAND */
  61 # define APOLLON_24XX_GPMC_CONFIG1_0    0x00000001
  62 # define APOLLON_24XX_GPMC_CONFIG2_0    0x000c1000
  63 # define APOLLON_24XX_GPMC_CONFIG3_0    0x00030400
  64 # define APOLLON_24XX_GPMC_CONFIG4_0    0x0b841006
  65 # define APOLLON_24XX_GPMC_CONFIG5_0    0x020f0c11
  66 # define APOLLON_24XX_GPMC_CONFIG6_0    0x00000000
  67 # define APOLLON_24XX_GPMC_CONFIG7_0    (0x00000e40|(APOLLON_CS0_BASE >> 24))
  68
  69 /* CS1: Ethernet */
  70 # define APOLLON_24XX_GPMC_CONFIG1_1    0x00011203
  71 # define APOLLON_24XX_GPMC_CONFIG2_1    0x001F1F01
  72 # define APOLLON_24XX_GPMC_CONFIG3_1    0x00080803
  73 # define APOLLON_24XX_GPMC_CONFIG4_1    0x1C0b1C0a
  74 # define APOLLON_24XX_GPMC_CONFIG5_1    0x041F1F1F
  75 # define APOLLON_24XX_GPMC_CONFIG6_1    0x000004C4
  76 # define APOLLON_24XX_GPMC_CONFIG7_1    (0x00000F40|(APOLLON_CS1_BASE >> 24))
  77
  78 /* CS2: OneNAND */
  79 /* It's same as CS0 */
  80 # define APOLLON_24XX_GPMC_CONFIG7_2    (0x00000e40|(APOLLON_CS2_BASE >> 24))
  81
  82 /* CS3: NOR */
  83 #ifdef ASYNC_NOR
  84 # define APOLLON_24XX_GPMC_CONFIG1_3    0x00021201
  85 # define APOLLON_24XX_GPMC_CONFIG2_3    0x00121601
  86 # define APOLLON_24XX_GPMC_CONFIG3_3    0x00040401
  87 # define APOLLON_24XX_GPMC_CONFIG4_3    0x12061605
  88 # define APOLLON_24XX_GPMC_CONFIG5_3    0x01151317
  89 #else
  90 # define SYNC_NOR_VALUE                 0x24aaa
  91 # define APOLLON_24XX_GPMC_CONFIG1_3    0xe5011211
  92 # define APOLLON_24XX_GPMC_CONFIG2_3    0x00090b01
  93 # define APOLLON_24XX_GPMC_CONFIG3_3    0x00020201
  94 # define APOLLON_24XX_GPMC_CONFIG4_3    0x09030b03
  95 # define APOLLON_24XX_GPMC_CONFIG5_3    0x010a0a0c
  96 #endif /* ASYNC_NOR */
  97 # define APOLLON_24XX_GPMC_CONFIG6_3    0x00000000
  98 # define APOLLON_24XX_GPMC_CONFIG7_3    (0x00000e40|(APOLLON_CS3_BASE >> 24))
  99 #endif /* endif PRCM_CONFIG_I */
 100
 101 #ifdef PRCM_CONFIG_II           /* L3 at 100MHz */
 102 /* CS0: OneNAND */
 103 # define APOLLON_24XX_GPMC_CONFIG1_0    0x00000001
 104 # define APOLLON_24XX_GPMC_CONFIG2_0    0x00081080
 105 # define APOLLON_24XX_GPMC_CONFIG3_0    0x00030300
 106 # define APOLLON_24XX_GPMC_CONFIG4_0    0x08041004
 107 # define APOLLON_24XX_GPMC_CONFIG5_0    0x020b0910
 108 # define APOLLON_24XX_GPMC_CONFIG6_0    0x00000000
 109 # define APOLLON_24XX_GPMC_CONFIG7_0    (0x00000C40|(APOLLON_CS0_BASE >> 24))
 110
 111 /* CS1: ethernet */
 112 # define APOLLON_24XX_GPMC_CONFIG1_1    0x00401203
 113 # define APOLLON_24XX_GPMC_CONFIG2_1    0x001F1F01
 114 # define APOLLON_24XX_GPMC_CONFIG3_1    0x00080803
 115 # define APOLLON_24XX_GPMC_CONFIG4_1    0x1C091C09
 116 # define APOLLON_24XX_GPMC_CONFIG5_1    0x041F1F1F
 117 # define APOLLON_24XX_GPMC_CONFIG6_1    0x000004C4
 118 # define APOLLON_24XX_GPMC_CONFIG7_1    (0x00000F40|(APOLLON_CS1_BASE >> 24))
 119
 120 /* CS2: OneNAND */
 121 /* It's same as CS0 */
 122 # define APOLLON_24XX_GPMC_CONFIG7_2    (0x00000e40|(APOLLON_CS2_BASE >> 24))
 123
 124 /* CS3: NOR */
 125 #define ASYNC_NOR
 126 #ifdef ASYNC_NOR
 127 # define APOLLON_24XX_GPMC_CONFIG1_3    0x00021201
 128 # define APOLLON_24XX_GPMC_CONFIG2_3    0x00121601
 129 # define APOLLON_24XX_GPMC_CONFIG3_3    0x00040401
 130 # define APOLLON_24XX_GPMC_CONFIG4_3    0x12061605
 131 # define APOLLON_24XX_GPMC_CONFIG5_3    0x01151317
 132 #else
 133 # define SYNC_NOR_VALUE                 0x24aaa
 134 # define APOLLON_24XX_GPMC_CONFIG1_3    0xe1001202
 135 # define APOLLON_24XX_GPMC_CONFIG2_3    0x00151501
 136 # define APOLLON_24XX_GPMC_CONFIG3_3    0x00050501
 137 # define APOLLON_24XX_GPMC_CONFIG4_3    0x0e070e07
 138 # define APOLLON_24XX_GPMC_CONFIG5_3    0x01131F1F
 139 #endif /* ASYNC_NOR */
 140 # define APOLLON_24XX_GPMC_CONFIG6_3    0x00000000
 141 # define APOLLON_24XX_GPMC_CONFIG7_3    (0x00000C40|(APOLLON_CS3_BASE >> 24))
 142 #endif /* endif PRCM_CONFIG_II */
 143
 144 #ifdef PRCM_CONFIG_III          /* L3 at 133MHz */
 145 # ifdef CONFIG_SYS_NAND_BOOT
 146 #  define APOLLON_24XX_GPMC_CONFIG1_0   0x0
 147 #  define APOLLON_24XX_GPMC_CONFIG2_0   0x00141400
 148 #  define APOLLON_24XX_GPMC_CONFIG3_0   0x00141400
 149 #  define APOLLON_24XX_GPMC_CONFIG4_0   0x0F010F01
 150 #  define APOLLON_24XX_GPMC_CONFIG5_0   0x010C1414
 151 #  define APOLLON_24XX_GPMC_CONFIG6_0   0x00000A80
 152 # else /* NOR boot */
 153 #  define APOLLON_24XX_GPMC_CONFIG1_0   0x3
 154 #  define APOLLON_24XX_GPMC_CONFIG2_0   0x00151501
 155 #  define APOLLON_24XX_GPMC_CONFIG3_0   0x00060602
 156 #  define APOLLON_24XX_GPMC_CONFIG4_0   0x10081008
 157 #  define APOLLON_24XX_GPMC_CONFIG5_0   0x01131F1F
 158 #  define APOLLON_24XX_GPMC_CONFIG6_0   0x000004c4
 159 # endif /* endif CONFIG_SYS_NAND_BOOT */
 160 # define APOLLON_24XX_GPMC_CONFIG7_0    (0x00000C40|(APOLLON_CS0_BASE >> 24))
 161 # define APOLLON_24XX_GPMC_CONFIG1_1    0x00011000
 162 # define APOLLON_24XX_GPMC_CONFIG2_1    0x001f1f01
 163 # define APOLLON_24XX_GPMC_CONFIG3_1    0x00080803
 164 # define APOLLON_24XX_GPMC_CONFIG4_1    0x1C091C09
 165 # define APOLLON_24XX_GPMC_CONFIG5_1    0x041f1F1F
 166 # define APOLLON_24XX_GPMC_CONFIG6_1    0x000004C4
 167 # define APOLLON_24XX_GPMC_CONFIG7_1    (0x00000F40|(APOLLON_CS1_BASE >> 24))
 168 #endif /* endif CONFIG_SYS_PRCM_III */
 169
 170 #endif /* endif _APOLLON_OMAP24XX_MEM_H_ */