board/aristainetos/clocks.cfg

   1 /*
   2  * Copyright (C) 2013 Boundary Devices
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  * Device Configuration Data (DCD)
   7  *
   8  * Each entry must have the format:
   9  * Addr-type           Address        Value
  10  *
  11  * where:
  12  *      Addr-type register length (1,2 or 4 bytes)
  13  *      Address   absolute address of the register
  14  *      value     value to be stored in the register
  15  */
  16
  17 /* set the default clock gate to save power */
  18 DATA 4, CCM_CCGR0, 0x00c03f3f
  19 DATA 4, CCM_CCGR1, 0x0030fcff
  20 DATA 4, CCM_CCGR2, 0x0fffcfc0
  21 DATA 4, CCM_CCGR3, 0x3ff0300f
  22 DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */
  23 DATA 4, CCM_CCGR5, 0x0f0000c3
  24 DATA 4, CCM_CCGR6, 0x000003ff