board/armltd/vexpress/vexpress_common.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
   8  *
   9  * (C) Copyright 2003
  10  * Texas Instruments, <www.ti.com>
  11  * Kshitij Gupta <Kshitij@ti.com>
  12  *
  13  * (C) Copyright 2004
  14  * ARM Ltd.
  15  * Philippe Robin, <philippe.robin@arm.com>
  16  *
  17  * SPDX-License-Identifier:     GPL-2.0+
  18  */
  19 #include <common.h>
  20 #include <malloc.h>
  21 #include <errno.h>
  22 #include <netdev.h>
  23 #include <asm/io.h>
  24 #include <asm/mach-types.h>
  25 #include <asm/arch/systimer.h>
  26 #include <asm/arch/sysctrl.h>
  27 #include <asm/arch/wdt.h>
  28 #include "../drivers/mmc/arm_pl180_mmci.h"
  29
  30 static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
  31 static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
  32
  33 static void flash__init(void);
  34 static void vexpress_timer_init(void);
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
  38 void show_boot_progress(int progress)
  39 {
  40         printf("Boot reached stage %d\n", progress);
  41 }
  42 #endif
  43
  44 static inline void delay(ulong loops)
  45 {
  46         __asm__ volatile ("1:\n"
  47                 "subs %0, %1, #1\n"
  48                 "bne 1b" : "=r" (loops) : "0" (loops));
  49 }
  50
  51 int board_init(void)
  52 {
  53         gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  54         gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
  55         gd->flags = 0;
  56
  57         icache_enable();
  58         flash__init();
  59         vexpress_timer_init();
  60
  61         return 0;
  62 }
  63
  64 int board_eth_init(bd_t *bis)
  65 {
  66         int rc = 0;
  67 #ifdef CONFIG_SMC911X
  68         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  69 #endif
  70         return rc;
  71 }
  72
  73 int cpu_mmc_init(bd_t *bis)
  74 {
  75         int rc = 0;
  76         (void) bis;
  77 #ifdef CONFIG_ARM_PL180_MMCI
  78         struct pl180_mmc_host *host;
  79         struct mmc *mmc;
  80
  81         host = malloc(sizeof(struct pl180_mmc_host));
  82         if (!host)
  83                 return -ENOMEM;
  84         memset(host, 0, sizeof(*host));
  85
  86         strcpy(host->name, "MMC");
  87         host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
  88         host->pwr_init = INIT_PWR;
  89         host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
  90         host->voltages = VOLTAGE_WINDOW_MMC;
  91         host->caps = 0;
  92         host->clock_in = ARM_MCLK;
  93         host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
  94         host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
  95         rc = arm_pl180_mmci_init(host, &mmc);
  96 #endif
  97         return rc;
  98 }
  99
 100 static void flash__init(void)
 101 {
 102         /* Setup the sytem control register to allow writing to flash */
 103         writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
 104                &sysctrl_base->scflashctrl);
 105 }
 106
 107 int dram_init(void)
 108 {
 109         gd->ram_size =
 110                 get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
 111         return 0;
 112 }
 113
 114 int dram_init_banksize(void)
 115 {
 116         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 117         gd->bd->bi_dram[0].size =
 118                         get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 119         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 120         gd->bd->bi_dram[1].size =
 121                         get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
 122
 123         return 0;
 124 }
 125
 126 /*
 127  * Start timer:
 128  *    Setup a 32 bit timer, running at 1KHz
 129  *    Versatile Express Motherboard provides 1 MHz timer
 130  */
 131 static void vexpress_timer_init(void)
 132 {
 133         /*
 134          * Set clock frequency in system controller:
 135          *   VEXPRESS_REFCLK is 32KHz
 136          *   VEXPRESS_TIMCLK is 1MHz
 137          */
 138         writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
 139                SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
 140                readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
 141
 142         /*
 143          * Set Timer0 to be:
 144          *   Enabled, free running, no interrupt, 32-bit, wrapping
 145          */
 146         writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
 147         writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
 148         writel(SYSTIMER_EN | SYSTIMER_32BIT |
 149                readl(&systimer_base->timer0control),
 150                &systimer_base->timer0control);
 151 }
 152
 153 int v2m_cfg_write(u32 devfn, u32 data)
 154 {
 155         /* Configuration interface broken? */
 156         u32 val;
 157
 158         devfn |= SYS_CFG_START | SYS_CFG_WRITE;
 159
 160         val = readl(V2M_SYS_CFGSTAT);
 161         writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
 162
 163         writel(data, V2M_SYS_CFGDATA);
 164         writel(devfn, V2M_SYS_CFGCTRL);
 165
 166         do {
 167                 val = readl(V2M_SYS_CFGSTAT);
 168         } while (val == 0);
 169
 170         return !!(val & SYS_CFG_ERR);
 171 }
 172
 173 /* Use the ARM Watchdog System to cause reset */
 174 void reset_cpu(ulong addr)
 175 {
 176         if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
 177                 printf("Unable to reboot\n");
 178 }
 179
 180 void lowlevel_init(void)
 181 {
 182 }
 183
 184 ulong get_board_rev(void){
 185         return readl((u32 *)SYS_ID);
 186 }
 187
 188 #ifdef CONFIG_ARMV7_NONSEC
 189 /* Setting the address at which secondary cores start from.
 190  * Versatile Express uses one address for all cores, so ignore corenr
 191  */
 192 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 193 {
 194         /* The SYSFLAGS register on VExpress needs to be cleared first
 195          * by writing to the next address, since any writes to the address
 196          * at offset 0 will only be ORed in
 197          */
 198         writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
 199         writel(addr, CONFIG_SYSFLAGS_ADDR);
 200 }
 201 #endif