board/atmel/at91sam9260ek/at91sam9260ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/at91sam9260_matrix.h>
  12 #include <asm/arch/at91sam9_smc.h>
  13 #include <asm/arch/at91_common.h>
  14 #include <asm/arch/at91_pmc.h>
  15 #include <asm/arch/at91_rstc.h>
  16 #include <asm/arch/gpio.h>
  17 #include <atmel_mci.h>
  18
  19 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  20 # include <net.h>
  21 #endif
  22 #include <netdev.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 /* ------------------------------------------------------------------------- */
  27 /*
  28  * Miscelaneous platform dependent initialisations
  29  */
  30
  31 #ifdef CONFIG_CMD_NAND
  32 static void at91sam9260ek_nand_hw_init(void)
  33 {
  34         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  35         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  36         unsigned long csa;
  37
  38         /* Assign CS3 to NAND/SmartMedia Interface */
  39         csa = readl(&matrix->ebicsa);
  40         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  41         writel(csa, &matrix->ebicsa);
  42
  43         /* Configure SMC CS3 for NAND/SmartMedia */
  44         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  45                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  46                 &smc->cs[3].setup);
  47         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  48                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  49                 &smc->cs[3].pulse);
  50         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  51                 &smc->cs[3].cycle);
  52         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  53                 AT91_SMC_MODE_EXNW_DISABLE |
  54 #ifdef CONFIG_SYS_NAND_DBW_16
  55                 AT91_SMC_MODE_DBW_16 |
  56 #else /* CONFIG_SYS_NAND_DBW_8 */
  57                 AT91_SMC_MODE_DBW_8 |
  58 #endif
  59                 AT91_SMC_MODE_TDF_CYCLE(2),
  60                 &smc->cs[3].mode);
  61
  62         /* Configure RDY/BSY */
  63         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  64
  65         /* Enable NandFlash */
  66         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  67
  68 }
  69 #endif
  70
  71 #ifdef CONFIG_MACB
  72 static void at91sam9260ek_macb_hw_init(void)
  73 {
  74         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  75         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  76         struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
  77         unsigned long erstl;
  78
  79         /* Enable EMAC clock */
  80         writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  81
  82         /*
  83          * Disable pull-up on:
  84          *      RXDV (PA17) => PHY normal mode (not Test mode)
  85          *      ERX0 (PA14) => PHY ADDR0
  86          *      ERX1 (PA15) => PHY ADDR1
  87          *      ERX2 (PA25) => PHY ADDR2
  88          *      ERX3 (PA26) => PHY ADDR3
  89          *      ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
  90          *
  91          * PHY has internal pull-down
  92          */
  93         writel(pin_to_mask(AT91_PIN_PA14) |
  94                 pin_to_mask(AT91_PIN_PA15) |
  95                 pin_to_mask(AT91_PIN_PA17) |
  96                 pin_to_mask(AT91_PIN_PA25) |
  97                 pin_to_mask(AT91_PIN_PA26) |
  98                 pin_to_mask(AT91_PIN_PA28),
  99                 &pioa->pudr);
 100
 101         erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
 102
 103         /* Need to reset PHY -> 500ms reset */
 104         writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
 105                 AT91_RSTC_MR_URSTEN, &rstc->mr);
 106
 107         writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 108
 109         /* Wait for end hardware reset */
 110         while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
 111                 ;
 112
 113         /* Restore NRST value */
 114         writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
 115                 &rstc->mr);
 116
 117         /* Re-enable pull-up */
 118         writel(pin_to_mask(AT91_PIN_PA14) |
 119                 pin_to_mask(AT91_PIN_PA15) |
 120                 pin_to_mask(AT91_PIN_PA17) |
 121                 pin_to_mask(AT91_PIN_PA25) |
 122                 pin_to_mask(AT91_PIN_PA26) |
 123                 pin_to_mask(AT91_PIN_PA28),
 124                 &pioa->puer);
 125
 126         /* Initialize EMAC=MACB hardware */
 127         at91_macb_hw_init();
 128 }
 129 #endif
 130
 131 #ifdef CONFIG_GENERIC_ATMEL_MCI
 132 int board_mmc_init(bd_t *bd)
 133 {
 134         at91_mci_hw_init();
 135
 136         return atmel_mci_init((void *)ATMEL_BASE_MCI);
 137 }
 138 #endif
 139
 140 int board_early_init_f(void)
 141 {
 142         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 143
 144         /* Enable clocks for all PIOs */
 145         writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
 146                 (1 << ATMEL_ID_PIOC),
 147                 &pmc->pcer);
 148
 149         return 0;
 150 }
 151
 152 int board_init(void)
 153 {
 154         /* adress of boot parameters */
 155         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 156
 157         at91_seriald_hw_init();
 158 #ifdef CONFIG_CMD_NAND
 159         at91sam9260ek_nand_hw_init();
 160 #endif
 161 #ifdef CONFIG_HAS_DATAFLASH
 162         at91_spi0_hw_init((1 << 0) | (1 << 1));
 163 #endif
 164 #ifdef CONFIG_MACB
 165         at91sam9260ek_macb_hw_init();
 166 #endif
 167
 168         return 0;
 169 }
 170
 171 int dram_init(void)
 172 {
 173         gd->ram_size = get_ram_size(
 174                 (void *)CONFIG_SYS_SDRAM_BASE,
 175                 CONFIG_SYS_SDRAM_SIZE);
 176         return 0;
 177 }
 178
 179 #ifdef CONFIG_RESET_PHY_R
 180 void reset_phy(void)
 181 {
 182 }
 183 #endif
 184
 185 int board_eth_init(bd_t *bis)
 186 {
 187         int rc = 0;
 188 #ifdef CONFIG_MACB
 189         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
 190 #endif
 191         return rc;
 192 }