board/atmel/at91sam9261ek/at91sam9261ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/at91sam9261.h>
  27 #include <asm/arch/at91sam9261_matrix.h>
  28 #include <asm/arch/at91sam9_smc.h>
  29 #include <asm/arch/at91_common.h>
  30 #include <asm/arch/at91_pmc.h>
  31 #include <asm/arch/at91_rstc.h>
  32 #include <asm/arch/gpio.h>
  33 #include <asm/arch/io.h>
  34 #include <lcd.h>
  35 #include <atmel_lcdc.h>
  36 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
  37 #include <net.h>
  38 #endif
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 /* ------------------------------------------------------------------------- */
  43 /*
  44  * Miscelaneous platform dependent initialisations
  45  */
  46
  47 #ifdef CONFIG_CMD_NAND
  48 static void at91sam9261ek_nand_hw_init(void)
  49 {
  50         unsigned long csa;
  51
  52         /* Enable CS3 */
  53         csa = at91_sys_read(AT91_MATRIX_EBICSA);
  54         at91_sys_write(AT91_MATRIX_EBICSA,
  55                        csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  56
  57         /* Configure SMC CS3 for NAND/SmartMedia */
  58         at91_sys_write(AT91_SMC_SETUP(3),
  59                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  60                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  61         at91_sys_write(AT91_SMC_PULSE(3),
  62                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  63                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  64         at91_sys_write(AT91_SMC_CYCLE(3),
  65                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  66         at91_sys_write(AT91_SMC_MODE(3),
  67                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  68                        AT91_SMC_EXNWMODE_DISABLE |
  69 #ifdef CONFIG_SYS_NAND_DBW_16
  70                        AT91_SMC_DBW_16 |
  71 #else /* CONFIG_SYS_NAND_DBW_8 */
  72                        AT91_SMC_DBW_8 |
  73 #endif
  74                        AT91_SMC_TDF_(2));
  75
  76         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
  77
  78         /* Configure RDY/BSY */
  79         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  80
  81         /* Enable NandFlash */
  82         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  83
  84         at91_set_A_periph(AT91_PIN_PC0, 0);     /* NANDOE */
  85         at91_set_A_periph(AT91_PIN_PC1, 0);     /* NANDWE */
  86 }
  87 #endif
  88
  89 #ifdef CONFIG_DRIVER_DM9000
  90 static void at91sam9261ek_dm9000_hw_init(void)
  91 {
  92         /* Configure SMC CS2 for DM9000 */
  93         at91_sys_write(AT91_SMC_SETUP(2),
  94                        AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
  95                        AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
  96         at91_sys_write(AT91_SMC_PULSE(2),
  97                        AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
  98                        AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
  99         at91_sys_write(AT91_SMC_CYCLE(2),
 100                        AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
 101         at91_sys_write(AT91_SMC_MODE(2),
 102                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 103                        AT91_SMC_EXNWMODE_DISABLE |
 104                        AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
 105                        AT91_SMC_TDF_(1));
 106
 107         /* Configure Reset signal as output */
 108         at91_set_gpio_output(AT91_PIN_PC10, 0);
 109
 110         /* Configure Interrupt pin as input, no pull-up */
 111         at91_set_gpio_input(AT91_PIN_PC11, 0);
 112 }
 113 #endif
 114
 115 #ifdef CONFIG_LCD
 116 vidinfo_t panel_info = {
 117         vl_col:         240,
 118         vl_row:         320,
 119         vl_clk:         4965000,
 120         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 121                         ATMEL_LCDC_INVFRAME_INVERTED,
 122         vl_bpix:        3,
 123         vl_tft:         1,
 124         vl_hsync_len:   5,
 125         vl_left_margin: 1,
 126         vl_right_margin:33,
 127         vl_vsync_len:   1,
 128         vl_upper_margin:1,
 129         vl_lower_margin:0,
 130         mmio:           AT91SAM9261_LCDC_BASE,
 131 };
 132
 133 void lcd_enable(void)
 134 {
 135         at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
 136 }
 137
 138 void lcd_disable(void)
 139 {
 140         at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
 141 }
 142
 143 static void at91sam9261ek_lcd_hw_init(void)
 144 {
 145         at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
 146         at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
 147         at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
 148         at91_set_A_periph(AT91_PIN_PB4, 0);     /* LCDCC */
 149         at91_set_A_periph(AT91_PIN_PB7, 0);     /* LCDD2 */
 150         at91_set_A_periph(AT91_PIN_PB8, 0);     /* LCDD3 */
 151         at91_set_A_periph(AT91_PIN_PB9, 0);     /* LCDD4 */
 152         at91_set_A_periph(AT91_PIN_PB10, 0);    /* LCDD5 */
 153         at91_set_A_periph(AT91_PIN_PB11, 0);    /* LCDD6 */
 154         at91_set_A_periph(AT91_PIN_PB12, 0);    /* LCDD7 */
 155         at91_set_A_periph(AT91_PIN_PB15, 0);    /* LCDD10 */
 156         at91_set_A_periph(AT91_PIN_PB16, 0);    /* LCDD11 */
 157         at91_set_A_periph(AT91_PIN_PB17, 0);    /* LCDD12 */
 158         at91_set_A_periph(AT91_PIN_PB18, 0);    /* LCDD13 */
 159         at91_set_A_periph(AT91_PIN_PB19, 0);    /* LCDD14 */
 160         at91_set_A_periph(AT91_PIN_PB20, 0);    /* LCDD15 */
 161         at91_set_B_periph(AT91_PIN_PB23, 0);    /* LCDD18 */
 162         at91_set_B_periph(AT91_PIN_PB24, 0);    /* LCDD19 */
 163         at91_set_B_periph(AT91_PIN_PB25, 0);    /* LCDD20 */
 164         at91_set_B_periph(AT91_PIN_PB26, 0);    /* LCDD21 */
 165         at91_set_B_periph(AT91_PIN_PB27, 0);    /* LCDD22 */
 166         at91_set_B_periph(AT91_PIN_PB28, 0);    /* LCDD23 */
 167
 168         at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
 169
 170         gd->fb_base = AT91SAM9261_SRAM_BASE;
 171 }
 172
 173 #ifdef CONFIG_LCD_INFO
 174 #include <nand.h>
 175 #include <version.h>
 176
 177 void lcd_show_board_info(void)
 178 {
 179         ulong dram_size, nand_size;
 180         int i;
 181         char temp[32];
 182
 183         lcd_printf ("%s\n", U_BOOT_VERSION);
 184         lcd_printf ("(C) 2008 ATMEL Corp\n");
 185         lcd_printf ("at91support@atmel.com\n");
 186         lcd_printf ("%s CPU at %s MHz\n",
 187                 AT91_CPU_NAME,
 188                 strmhz(temp, AT91_CPU_CLOCK));
 189
 190         dram_size = 0;
 191         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 192                 dram_size += gd->bd->bi_dram[i].size;
 193         nand_size = 0;
 194         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 195                 nand_size += nand_info[i].size;
 196         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 197                 dram_size >> 20,
 198                 nand_size >> 20 );
 199 }
 200 #endif /* CONFIG_LCD_INFO */
 201 #endif
 202
 203 int board_init(void)
 204 {
 205         /* Enable Ctrlc */
 206         console_init_f();
 207
 208         /* arch number of AT91SAM9261EK-Board */
 209         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
 210         /* adress of boot parameters */
 211         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 212
 213         at91_serial_hw_init();
 214 #ifdef CONFIG_CMD_NAND
 215         at91sam9261ek_nand_hw_init();
 216 #endif
 217 #ifdef CONFIG_HAS_DATAFLASH
 218         at91_spi0_hw_init(1 << 0);
 219 #endif
 220 #ifdef CONFIG_DRIVER_DM9000
 221         at91sam9261ek_dm9000_hw_init();
 222 #endif
 223 #ifdef CONFIG_LCD
 224         at91sam9261ek_lcd_hw_init();
 225 #endif
 226         return 0;
 227 }
 228
 229 int dram_init(void)
 230 {
 231         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 232         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 233         return 0;
 234 }
 235
 236 #ifdef CONFIG_RESET_PHY_R
 237 void reset_phy(void)
 238 {
 239 #ifdef CONFIG_DRIVER_DM9000
 240         /*
 241          * Initialize ethernet HW addr prior to starting Linux,
 242          * needed for nfsroot
 243          */
 244         eth_init(gd->bd);
 245 #endif
 246 }
 247 #endif