board/atmel/at91sam9263ek/at91sam9263ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/sizes.h>
  11 #include <asm/arch/at91sam9263.h>
  12 #include <asm/arch/at91sam9_smc.h>
  13 #include <asm/arch/at91_common.h>
  14 #include <asm/arch/at91_pmc.h>
  15 #include <asm/arch/at91_rstc.h>
  16 #include <asm/arch/at91_matrix.h>
  17 #include <asm/arch/at91_pio.h>
  18 #include <asm/arch/clk.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/hardware.h>
  22 #include <lcd.h>
  23 #include <atmel_lcdc.h>
  24 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  25 #include <net.h>
  26 #endif
  27 #include <netdev.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 /* ------------------------------------------------------------------------- */
  32 /*
  33  * Miscelaneous platform dependent initialisations
  34  */
  35
  36 #ifdef CONFIG_CMD_NAND
  37 static void at91sam9263ek_nand_hw_init(void)
  38 {
  39         unsigned long csa;
  40         at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
  41         at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  42         at91_pmc_t    *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
  43
  44         /* Enable CS3 */
  45         csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  46         writel(csa, &matrix->csa[0]);
  47
  48         /* Enable CS3 */
  49
  50         /* Configure SMC CS3 for NAND/SmartMedia */
  51         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  52                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  53                 &smc->cs[3].setup);
  54
  55         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  56                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  57                 &smc->cs[3].pulse);
  58
  59         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  60                 &smc->cs[3].cycle);
  61         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  62                 AT91_SMC_MODE_EXNW_DISABLE |
  63 #ifdef CONFIG_SYS_NAND_DBW_16
  64                        AT91_SMC_MODE_DBW_16 |
  65 #else /* CONFIG_SYS_NAND_DBW_8 */
  66                        AT91_SMC_MODE_DBW_8 |
  67 #endif
  68                        AT91_SMC_MODE_TDF_CYCLE(2),
  69                 &smc->cs[3].mode);
  70
  71         writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE,
  72                 &pmc->pcer);
  73
  74         /* Configure RDY/BSY */
  75         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  76
  77         /* Enable NandFlash */
  78         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  79 }
  80 #endif
  81
  82 #ifdef CONFIG_MACB
  83 static void at91sam9263ek_macb_hw_init(void)
  84 {
  85         unsigned long   erstl;
  86         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
  87         at91_pio_t      *pio    = (at91_pio_t *) ATMEL_BASE_PIO;
  88         at91_rstc_t     *rstc   = (at91_rstc_t *) ATMEL_BASE_RSTC;
  89         /* Enable clock */
  90         writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  91
  92         /*
  93          * Disable pull-up on:
  94          *      RXDV (PC25) => PHY normal mode (not Test mode)
  95          *      ERX0 (PE25) => PHY ADDR0
  96          *      ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
  97          *
  98          * PHY has internal pull-down
  99          */
 100
 101         writel(1 << 25, &pio->pioc.pudr);
 102         writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
 103
 104         erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
 105
 106         /* Need to reset PHY -> 500ms reset */
 107         writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
 108                 AT91_RSTC_MR_URSTEN, &rstc->mr);
 109
 110         writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 111         /* Wait for end hardware reset */
 112         while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
 113                 ;
 114
 115         /* Restore NRST value */
 116         writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
 117
 118         /* Re-enable pull-up */
 119         writel(1 << 25, &pio->pioc.puer);
 120         writel((1 << 25) | (1 <<26), &pio->pioe.puer);
 121
 122         at91_macb_hw_init();
 123 }
 124 #endif
 125
 126 #ifdef CONFIG_LCD
 127 vidinfo_t panel_info = {
 128         vl_col:         240,
 129         vl_row:         320,
 130         vl_clk:         4965000,
 131         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 132                         ATMEL_LCDC_INVFRAME_INVERTED,
 133         vl_bpix:        3,
 134         vl_tft:         1,
 135         vl_hsync_len:   5,
 136         vl_left_margin: 1,
 137         vl_right_margin:33,
 138         vl_vsync_len:   1,
 139         vl_upper_margin:1,
 140         vl_lower_margin:0,
 141         mmio:           ATMEL_BASE_LCDC,
 142 };
 143
 144 void lcd_enable(void)
 145 {
 146         at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
 147 }
 148
 149 void lcd_disable(void)
 150 {
 151         at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
 152 }
 153
 154 static void at91sam9263ek_lcd_hw_init(void)
 155 {
 156         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 157
 158         at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* LCDHSYNC */
 159         at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* LCDDOTCK */
 160         at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* LCDDEN */
 161         at91_set_b_periph(AT91_PIO_PORTB, 9, 0);        /* LCDCC */
 162         at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* LCDD2 */
 163         at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* LCDD3 */
 164         at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* LCDD4 */
 165         at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* LCDD5 */
 166         at91_set_a_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD6 */
 167         at91_set_a_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD7 */
 168         at91_set_a_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD10 */
 169         at91_set_a_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD11 */
 170         at91_set_a_periph(AT91_PIO_PORTC, 16, 0);       /* LCDD12 */
 171         at91_set_b_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD13 */
 172         at91_set_a_periph(AT91_PIO_PORTC, 18, 0);       /* LCDD14 */
 173         at91_set_a_periph(AT91_PIO_PORTC, 19, 0);       /* LCDD15 */
 174         at91_set_a_periph(AT91_PIO_PORTC, 22, 0);       /* LCDD18 */
 175         at91_set_a_periph(AT91_PIO_PORTC, 23, 0);       /* LCDD19 */
 176         at91_set_a_periph(AT91_PIO_PORTC, 24, 0);       /* LCDD20 */
 177         at91_set_b_periph(AT91_PIO_PORTC, 17, 0);       /* LCDD21 */
 178         at91_set_a_periph(AT91_PIO_PORTC, 26, 0);       /* LCDD22 */
 179         at91_set_a_periph(AT91_PIO_PORTC, 27, 0);       /* LCDD23 */
 180
 181         writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
 182         gd->fb_base = ATMEL_BASE_SRAM0;
 183 }
 184
 185 #ifdef CONFIG_LCD_INFO
 186 #include <nand.h>
 187 #include <version.h>
 188
 189 #ifndef CONFIG_SYS_NO_FLASH
 190 extern flash_info_t flash_info[];
 191 #endif
 192
 193 void lcd_show_board_info(void)
 194 {
 195         ulong dram_size, nand_size;
 196 #ifndef CONFIG_SYS_NO_FLASH
 197         ulong flash_size;
 198 #endif
 199         int i;
 200         char temp[32];
 201
 202         lcd_printf ("%s\n", U_BOOT_VERSION);
 203         lcd_printf ("(C) 2008 ATMEL Corp\n");
 204         lcd_printf ("at91support@atmel.com\n");
 205         lcd_printf ("%s CPU at %s MHz\n",
 206                 ATMEL_CPU_NAME,
 207                 strmhz(temp, get_cpu_clk_rate()));
 208
 209         dram_size = 0;
 210         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 211                 dram_size += gd->bd->bi_dram[i].size;
 212         nand_size = 0;
 213         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 214                 nand_size += nand_info[i].size;
 215 #ifndef CONFIG_SYS_NO_FLASH
 216         flash_size = 0;
 217         for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 218                 flash_size += flash_info[i].size;
 219 #endif
 220         lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
 221                 dram_size >> 20,
 222                 nand_size >> 20 );
 223 #ifndef CONFIG_SYS_NO_FLASH
 224         lcd_printf (",\n  %ld MB NOR",
 225                 flash_size >> 20);
 226 #endif
 227         lcd_puts ("\n");
 228 }
 229 #endif /* CONFIG_LCD_INFO */
 230 #endif
 231
 232 int board_early_init_f(void)
 233 {
 234         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 235
 236         /* Enable clocks for all PIOs */
 237         writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
 238                 (1 << ATMEL_ID_PIOCDE),
 239                 &pmc->pcer);
 240
 241         at91_seriald_hw_init();
 242         return 0;
 243 }
 244
 245 int board_init(void)
 246 {
 247         /* arch number of AT91SAM9263EK-Board */
 248         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
 249         /* adress of boot parameters */
 250         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 251
 252 #ifdef CONFIG_CMD_NAND
 253         at91sam9263ek_nand_hw_init();
 254 #endif
 255 #ifdef CONFIG_HAS_DATAFLASH
 256         at91_set_pio_output(AT91_PIO_PORTE, 20, 1);     /* select spi0 clock */
 257         at91_spi0_hw_init(1 << 0);
 258 #endif
 259 #ifdef CONFIG_MACB
 260         at91sam9263ek_macb_hw_init();
 261 #endif
 262 #ifdef CONFIG_USB_OHCI_NEW
 263         at91_uhp_hw_init();
 264 #endif
 265 #ifdef CONFIG_LCD
 266         at91sam9263ek_lcd_hw_init();
 267 #endif
 268         return 0;
 269 }
 270
 271 int dram_init(void)
 272 {
 273         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 274                 CONFIG_SYS_SDRAM_SIZE);
 275
 276         return 0;
 277 }
 278
 279 #ifdef CONFIG_RESET_PHY_R
 280 void reset_phy(void)
 281 {
 282 }
 283 #endif
 284
 285 int board_eth_init(bd_t *bis)
 286 {
 287         int rc = 0;
 288 #ifdef CONFIG_MACB
 289         rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
 290 #endif
 291         return rc;
 292 }