board/atmel/at91sam9263ek/at91sam9263ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/sizes.h>
  27 #include <asm/arch/at91sam9263.h>
  28 #include <asm/arch/at91sam9263_matrix.h>
  29 #include <asm/arch/at91sam9_smc.h>
  30 #include <asm/arch/at91_common.h>
  31 #include <asm/arch/at91_pmc.h>
  32 #include <asm/arch/at91_rstc.h>
  33 #include <asm/arch/clk.h>
  34 #include <asm/arch/gpio.h>
  35 #include <asm/arch/io.h>
  36 #include <asm/arch/hardware.h>
  37 #include <lcd.h>
  38 #include <atmel_lcdc.h>
  39 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  40 #include <net.h>
  41 #endif
  42 #include <netdev.h>
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* ------------------------------------------------------------------------- */
  47 /*
  48  * Miscelaneous platform dependent initialisations
  49  */
  50
  51 #ifdef CONFIG_CMD_NAND
  52 static void at91sam9263ek_nand_hw_init(void)
  53 {
  54         unsigned long csa;
  55
  56         /* Enable CS3 */
  57         csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
  58         at91_sys_write(AT91_MATRIX_EBI0CSA,
  59                        csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
  60
  61         /* Configure SMC CS3 for NAND/SmartMedia */
  62         at91_sys_write(AT91_SMC_SETUP(3),
  63                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  64                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  65         at91_sys_write(AT91_SMC_PULSE(3),
  66                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  67                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  68         at91_sys_write(AT91_SMC_CYCLE(3),
  69                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  70         at91_sys_write(AT91_SMC_MODE(3),
  71                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  72                        AT91_SMC_EXNWMODE_DISABLE |
  73 #ifdef CONFIG_SYS_NAND_DBW_16
  74                        AT91_SMC_DBW_16 |
  75 #else /* CONFIG_SYS_NAND_DBW_8 */
  76                        AT91_SMC_DBW_8 |
  77 #endif
  78                        AT91_SMC_TDF_(2));
  79
  80         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
  81                                       1 << AT91SAM9263_ID_PIOCDE);
  82
  83         /* Configure RDY/BSY */
  84         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  85
  86         /* Enable NandFlash */
  87         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  88 }
  89 #endif
  90
  91 #ifdef CONFIG_MACB
  92 static void at91sam9263ek_macb_hw_init(void)
  93 {
  94         /* Enable clock */
  95         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
  96
  97         /*
  98          * Disable pull-up on:
  99          *      RXDV (PC25) => PHY normal mode (not Test mode)
 100          *      ERX0 (PE25) => PHY ADDR0
 101          *      ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
 102          *
 103          * PHY has internal pull-down
 104          */
 105         writel(pin_to_mask(AT91_PIN_PC25),
 106                pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
 107         writel(pin_to_mask(AT91_PIN_PE25) |
 108                pin_to_mask(AT91_PIN_PE26),
 109                pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
 110
 111         /* Need to reset PHY -> 500ms reset */
 112         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 113                                      (AT91_RSTC_ERSTL & (0x0D << 8)) |
 114                                      AT91_RSTC_URSTEN);
 115
 116         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 117
 118         /* Wait for end hardware reset */
 119         while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 120
 121         /* Restore NRST value */
 122         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 123                                      (AT91_RSTC_ERSTL & (0x0 << 8)) |
 124                                      AT91_RSTC_URSTEN);
 125
 126         /* Re-enable pull-up */
 127         writel(pin_to_mask(AT91_PIN_PC25),
 128                pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
 129         writel(pin_to_mask(AT91_PIN_PE25) |
 130                pin_to_mask(AT91_PIN_PE26),
 131                pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
 132
 133         at91_macb_hw_init();
 134 }
 135 #endif
 136
 137 #ifdef CONFIG_LCD
 138 vidinfo_t panel_info = {
 139         vl_col:         240,
 140         vl_row:         320,
 141         vl_clk:         4965000,
 142         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 143                         ATMEL_LCDC_INVFRAME_INVERTED,
 144         vl_bpix:        3,
 145         vl_tft:         1,
 146         vl_hsync_len:   5,
 147         vl_left_margin: 1,
 148         vl_right_margin:33,
 149         vl_vsync_len:   1,
 150         vl_upper_margin:1,
 151         vl_lower_margin:0,
 152         mmio:           AT91SAM9263_LCDC_BASE,
 153 };
 154
 155 void lcd_enable(void)
 156 {
 157         at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power up */
 158 }
 159
 160 void lcd_disable(void)
 161 {
 162         at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power down */
 163 }
 164
 165 static void at91sam9263ek_lcd_hw_init(void)
 166 {
 167         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
 168         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
 169         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
 170         at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
 171         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
 172         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
 173         at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
 174         at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
 175         at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
 176         at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
 177         at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
 178         at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 179         at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 180         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD13 */
 181         at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 182         at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 183         at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
 184         at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
 185         at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
 186         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD21 */
 187         at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
 188         at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
 189
 190         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
 191
 192         gd->fb_base = AT91SAM9263_SRAM0_BASE;
 193 }
 194
 195 #ifdef CONFIG_LCD_INFO
 196 #include <nand.h>
 197 #include <version.h>
 198
 199 #ifndef CONFIG_SYS_NO_FLASH
 200 extern flash_info_t flash_info[];
 201 #endif
 202
 203 void lcd_show_board_info(void)
 204 {
 205         ulong dram_size, nand_size;
 206 #ifndef CONFIG_SYS_NO_FLASH
 207         ulong flash_size;
 208 #endif
 209         int i;
 210         char temp[32];
 211
 212         lcd_printf ("%s\n", U_BOOT_VERSION);
 213         lcd_printf ("(C) 2008 ATMEL Corp\n");
 214         lcd_printf ("at91support@atmel.com\n");
 215         lcd_printf ("%s CPU at %s MHz\n",
 216                 AT91_CPU_NAME,
 217                 strmhz(temp, get_cpu_clk_rate()));
 218
 219         dram_size = 0;
 220         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 221                 dram_size += gd->bd->bi_dram[i].size;
 222         nand_size = 0;
 223         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 224                 nand_size += nand_info[i].size;
 225 #ifndef CONFIG_SYS_NO_FLASH
 226         flash_size = 0;
 227         for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 228                 flash_size += flash_info[i].size;
 229 #endif
 230         lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
 231                 dram_size >> 20,
 232                 nand_size >> 20 );
 233 #ifndef CONFIG_SYS_NO_FLASH
 234         lcd_printf (",\n  %ld MB NOR",
 235                 flash_size >> 20);
 236 #endif
 237         lcd_puts ("\n");
 238 }
 239 #endif /* CONFIG_LCD_INFO */
 240 #endif
 241
 242 int board_init(void)
 243 {
 244         /* Enable Ctrlc */
 245         console_init_f();
 246
 247         /* arch number of AT91SAM9263EK-Board */
 248         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
 249         /* adress of boot parameters */
 250         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 251
 252         at91_serial_hw_init();
 253 #ifdef CONFIG_CMD_NAND
 254         at91sam9263ek_nand_hw_init();
 255 #endif
 256 #ifdef CONFIG_HAS_DATAFLASH
 257         at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */
 258         at91_spi0_hw_init(1 << 0);
 259 #endif
 260 #ifdef CONFIG_MACB
 261         at91sam9263ek_macb_hw_init();
 262 #endif
 263 #ifdef CONFIG_USB_OHCI_NEW
 264         at91_uhp_hw_init();
 265 #endif
 266 #ifdef CONFIG_LCD
 267         at91sam9263ek_lcd_hw_init();
 268 #endif
 269         return 0;
 270 }
 271
 272 int dram_init(void)
 273 {
 274         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 275         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 276         return 0;
 277 }
 278
 279 #ifdef CONFIG_RESET_PHY_R
 280 void reset_phy(void)
 281 {
 282 #ifdef CONFIG_MACB
 283         /*
 284          * Initialize ethernet HW addr prior to starting Linux,
 285          * needed for nfsroot
 286          */
 287         eth_init(gd->bd);
 288 #endif
 289 }
 290 #endif
 291
 292 int board_eth_init(bd_t *bis)
 293 {
 294         int rc = 0;
 295 #ifdef CONFIG_MACB
 296         rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
 297 #endif
 298         return rc;
 299 }