2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/sizes.h>
27 #include <asm/arch/at91sam9263.h>
28 #include <asm/arch/at91sam9263_matrix.h>
29 #include <asm/arch/at91sam9_smc.h>
30 #include <asm/arch/at91_common.h>
31 #include <asm/arch/at91_pmc.h>
32 #include <asm/arch/at91_rstc.h>
33 #include <asm/arch/clk.h>
34 #include <asm/arch/gpio.h>
35 #include <asm/arch/io.h>
36 #include <asm/arch/hardware.h>
38 #include <atmel_lcdc.h>
39 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
44 DECLARE_GLOBAL_DATA_PTR
;
46 /* ------------------------------------------------------------------------- */
48 * Miscelaneous platform dependent initialisations
51 #ifdef CONFIG_CMD_NAND
52 static void at91sam9263ek_nand_hw_init(void)
57 csa
= at91_sys_read(AT91_MATRIX_EBI0CSA
);
58 at91_sys_write(AT91_MATRIX_EBI0CSA
,
59 csa
| AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA
);
61 /* Configure SMC CS3 for NAND/SmartMedia */
62 at91_sys_write(AT91_SMC_SETUP(3),
63 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
64 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
65 at91_sys_write(AT91_SMC_PULSE(3),
66 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
67 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
68 at91_sys_write(AT91_SMC_CYCLE(3),
69 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
70 at91_sys_write(AT91_SMC_MODE(3),
71 AT91_SMC_READMODE
| AT91_SMC_WRITEMODE
|
72 AT91_SMC_EXNWMODE_DISABLE
|
73 #ifdef CONFIG_SYS_NAND_DBW_16
75 #else /* CONFIG_SYS_NAND_DBW_8 */
80 at91_sys_write(AT91_PMC_PCER
, 1 << AT91SAM9263_ID_PIOA
|
81 1 << AT91SAM9263_ID_PIOCDE
);
83 /* Configure RDY/BSY */
84 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN
, 1);
86 /* Enable NandFlash */
87 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN
, 1);
92 static void at91sam9263ek_macb_hw_init(void)
95 at91_sys_write(AT91_PMC_PCER
, 1 << AT91SAM9263_ID_EMAC
);
99 * RXDV (PC25) => PHY normal mode (not Test mode)
100 * ERX0 (PE25) => PHY ADDR0
101 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
103 * PHY has internal pull-down
105 writel(pin_to_mask(AT91_PIN_PC25
),
106 pin_to_controller(AT91_PIN_PC0
) + PIO_PUDR
);
107 writel(pin_to_mask(AT91_PIN_PE25
) |
108 pin_to_mask(AT91_PIN_PE26
),
109 pin_to_controller(AT91_PIN_PE0
) + PIO_PUDR
);
111 /* Need to reset PHY -> 500ms reset */
112 at91_sys_write(AT91_RSTC_MR
, AT91_RSTC_KEY
|
113 (AT91_RSTC_ERSTL
& (0x0D << 8)) |
116 at91_sys_write(AT91_RSTC_CR
, AT91_RSTC_KEY
| AT91_RSTC_EXTRST
);
118 /* Wait for end hardware reset */
119 while (!(at91_sys_read(AT91_RSTC_SR
) & AT91_RSTC_NRSTL
));
121 /* Restore NRST value */
122 at91_sys_write(AT91_RSTC_MR
, AT91_RSTC_KEY
|
123 (AT91_RSTC_ERSTL
& (0x0 << 8)) |
126 /* Re-enable pull-up */
127 writel(pin_to_mask(AT91_PIN_PC25
),
128 pin_to_controller(AT91_PIN_PC0
) + PIO_PUER
);
129 writel(pin_to_mask(AT91_PIN_PE25
) |
130 pin_to_mask(AT91_PIN_PE26
),
131 pin_to_controller(AT91_PIN_PE0
) + PIO_PUER
);
138 vidinfo_t panel_info
= {
142 vl_sync
: ATMEL_LCDC_INVLINE_INVERTED
|
143 ATMEL_LCDC_INVFRAME_INVERTED
,
152 mmio
: AT91SAM9263_LCDC_BASE
,
155 void lcd_enable(void)
157 at91_set_gpio_value(AT91_PIN_PA30
, 1); /* power up */
160 void lcd_disable(void)
162 at91_set_gpio_value(AT91_PIN_PA30
, 0); /* power down */
165 static void at91sam9263ek_lcd_hw_init(void)
167 at91_set_A_periph(AT91_PIN_PC1
, 0); /* LCDHSYNC */
168 at91_set_A_periph(AT91_PIN_PC2
, 0); /* LCDDOTCK */
169 at91_set_A_periph(AT91_PIN_PC3
, 0); /* LCDDEN */
170 at91_set_B_periph(AT91_PIN_PB9
, 0); /* LCDCC */
171 at91_set_A_periph(AT91_PIN_PC6
, 0); /* LCDD2 */
172 at91_set_A_periph(AT91_PIN_PC7
, 0); /* LCDD3 */
173 at91_set_A_periph(AT91_PIN_PC8
, 0); /* LCDD4 */
174 at91_set_A_periph(AT91_PIN_PC9
, 0); /* LCDD5 */
175 at91_set_A_periph(AT91_PIN_PC10
, 0); /* LCDD6 */
176 at91_set_A_periph(AT91_PIN_PC11
, 0); /* LCDD7 */
177 at91_set_A_periph(AT91_PIN_PC14
, 0); /* LCDD10 */
178 at91_set_A_periph(AT91_PIN_PC15
, 0); /* LCDD11 */
179 at91_set_A_periph(AT91_PIN_PC16
, 0); /* LCDD12 */
180 at91_set_B_periph(AT91_PIN_PC12
, 0); /* LCDD13 */
181 at91_set_A_periph(AT91_PIN_PC18
, 0); /* LCDD14 */
182 at91_set_A_periph(AT91_PIN_PC19
, 0); /* LCDD15 */
183 at91_set_A_periph(AT91_PIN_PC22
, 0); /* LCDD18 */
184 at91_set_A_periph(AT91_PIN_PC23
, 0); /* LCDD19 */
185 at91_set_A_periph(AT91_PIN_PC24
, 0); /* LCDD20 */
186 at91_set_B_periph(AT91_PIN_PC17
, 0); /* LCDD21 */
187 at91_set_A_periph(AT91_PIN_PC26
, 0); /* LCDD22 */
188 at91_set_A_periph(AT91_PIN_PC27
, 0); /* LCDD23 */
190 at91_sys_write(AT91_PMC_PCER
, 1 << AT91SAM9263_ID_LCDC
);
192 gd
->fb_base
= AT91SAM9263_SRAM0_BASE
;
195 #ifdef CONFIG_LCD_INFO
199 void lcd_show_board_info(void)
201 ulong dram_size
, nand_size
;
205 lcd_printf ("%s\n", U_BOOT_VERSION
);
206 lcd_printf ("(C) 2008 ATMEL Corp\n");
207 lcd_printf ("at91support@atmel.com\n");
208 lcd_printf ("%s CPU at %s MHz\n",
210 strmhz(temp
, get_cpu_clk_rate()));
213 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++)
214 dram_size
+= gd
->bd
->bi_dram
[i
].size
;
216 for (i
= 0; i
< CONFIG_SYS_MAX_NAND_DEVICE
; i
++)
217 nand_size
+= nand_info
[i
].size
;
218 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
222 #endif /* CONFIG_LCD_INFO */
230 /* arch number of AT91SAM9263EK-Board */
231 gd
->bd
->bi_arch_number
= MACH_TYPE_AT91SAM9263EK
;
232 /* adress of boot parameters */
233 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
235 at91_serial_hw_init();
236 #ifdef CONFIG_CMD_NAND
237 at91sam9263ek_nand_hw_init();
239 #ifdef CONFIG_HAS_DATAFLASH
240 at91_set_gpio_output(AT91_PIN_PE20
, 1); /* select spi0 clock */
241 at91_spi0_hw_init(1 << 0);
244 at91sam9263ek_macb_hw_init();
246 #ifdef CONFIG_USB_OHCI_NEW
250 at91sam9263ek_lcd_hw_init();
257 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM
;
258 gd
->bd
->bi_dram
[0].size
= PHYS_SDRAM_SIZE
;
262 #ifdef CONFIG_RESET_PHY_R
267 * Initialize ethernet HW addr prior to starting Linux,
275 int board_eth_init(bd_t
*bis
)
279 rc
= macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC
, 0x00);