board/atmel/at91sam9263ek/at91sam9263ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/sizes.h>
  11 #include <asm/arch/at91sam9263.h>
  12 #include <asm/arch/at91sam9_smc.h>
  13 #include <asm/arch/at91_common.h>
  14 #include <asm/arch/at91_pmc.h>
  15 #include <asm/arch/at91_matrix.h>
  16 #include <asm/arch/at91_pio.h>
  17 #include <asm/arch/clk.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/hardware.h>
  21 #include <lcd.h>
  22 #include <atmel_lcdc.h>
  23 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  24 #include <net.h>
  25 #endif
  26 #include <netdev.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 /* ------------------------------------------------------------------------- */
  31 /*
  32  * Miscelaneous platform dependent initialisations
  33  */
  34
  35 #ifdef CONFIG_CMD_NAND
  36 static void at91sam9263ek_nand_hw_init(void)
  37 {
  38         unsigned long csa;
  39         at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
  40         at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  41         at91_pmc_t    *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
  42
  43         /* Enable CS3 */
  44         csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  45         writel(csa, &matrix->csa[0]);
  46
  47         /* Enable CS3 */
  48
  49         /* Configure SMC CS3 for NAND/SmartMedia */
  50         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  51                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  52                 &smc->cs[3].setup);
  53
  54         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  55                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  56                 &smc->cs[3].pulse);
  57
  58         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  59                 &smc->cs[3].cycle);
  60         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  61                 AT91_SMC_MODE_EXNW_DISABLE |
  62 #ifdef CONFIG_SYS_NAND_DBW_16
  63                        AT91_SMC_MODE_DBW_16 |
  64 #else /* CONFIG_SYS_NAND_DBW_8 */
  65                        AT91_SMC_MODE_DBW_8 |
  66 #endif
  67                        AT91_SMC_MODE_TDF_CYCLE(2),
  68                 &smc->cs[3].mode);
  69
  70         writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE,
  71                 &pmc->pcer);
  72
  73         /* Configure RDY/BSY */
  74         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  75
  76         /* Enable NandFlash */
  77         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  78 }
  79 #endif
  80
  81 #ifdef CONFIG_MACB
  82 static void at91sam9263ek_macb_hw_init(void)
  83 {
  84         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
  85         at91_pio_t      *pio    = (at91_pio_t *) ATMEL_BASE_PIO;
  86
  87         /* Enable clock */
  88         writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  89
  90         /*
  91          * Disable pull-up on:
  92          *      RXDV (PC25) => PHY normal mode (not Test mode)
  93          *      ERX0 (PE25) => PHY ADDR0
  94          *      ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
  95          *
  96          * PHY has internal pull-down
  97          */
  98         writel(1 << 25, &pio->pioc.pudr);
  99         writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
 100
 101         at91_phy_reset();
 102
 103         /* Re-enable pull-up */
 104         writel(1 << 25, &pio->pioc.puer);
 105         writel((1 << 25) | (1 <<26), &pio->pioe.puer);
 106
 107         at91_macb_hw_init();
 108 }
 109 #endif
 110
 111 #ifdef CONFIG_LCD
 112 vidinfo_t panel_info = {
 113         vl_col:         240,
 114         vl_row:         320,
 115         vl_clk:         4965000,
 116         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 117                         ATMEL_LCDC_INVFRAME_INVERTED,
 118         vl_bpix:        3,
 119         vl_tft:         1,
 120         vl_hsync_len:   5,
 121         vl_left_margin: 1,
 122         vl_right_margin:33,
 123         vl_vsync_len:   1,
 124         vl_upper_margin:1,
 125         vl_lower_margin:0,
 126         mmio:           ATMEL_BASE_LCDC,
 127 };
 128
 129 void lcd_enable(void)
 130 {
 131         at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
 132 }
 133
 134 void lcd_disable(void)
 135 {
 136         at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
 137 }
 138
 139 static void at91sam9263ek_lcd_hw_init(void)
 140 {
 141         at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 142
 143         at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* LCDHSYNC */
 144         at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* LCDDOTCK */
 145         at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* LCDDEN */
 146         at91_set_b_periph(AT91_PIO_PORTB, 9, 0);        /* LCDCC */
 147         at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* LCDD2 */
 148         at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* LCDD3 */
 149         at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* LCDD4 */
 150         at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* LCDD5 */
 151         at91_set_a_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD6 */
 152         at91_set_a_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD7 */
 153         at91_set_a_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD10 */
 154         at91_set_a_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD11 */
 155         at91_set_a_periph(AT91_PIO_PORTC, 16, 0);       /* LCDD12 */
 156         at91_set_b_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD13 */
 157         at91_set_a_periph(AT91_PIO_PORTC, 18, 0);       /* LCDD14 */
 158         at91_set_a_periph(AT91_PIO_PORTC, 19, 0);       /* LCDD15 */
 159         at91_set_a_periph(AT91_PIO_PORTC, 22, 0);       /* LCDD18 */
 160         at91_set_a_periph(AT91_PIO_PORTC, 23, 0);       /* LCDD19 */
 161         at91_set_a_periph(AT91_PIO_PORTC, 24, 0);       /* LCDD20 */
 162         at91_set_b_periph(AT91_PIO_PORTC, 17, 0);       /* LCDD21 */
 163         at91_set_a_periph(AT91_PIO_PORTC, 26, 0);       /* LCDD22 */
 164         at91_set_a_periph(AT91_PIO_PORTC, 27, 0);       /* LCDD23 */
 165
 166         writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
 167         gd->fb_base = ATMEL_BASE_SRAM0;
 168 }
 169
 170 #ifdef CONFIG_LCD_INFO
 171 #include <nand.h>
 172 #include <version.h>
 173
 174 #ifndef CONFIG_SYS_NO_FLASH
 175 extern flash_info_t flash_info[];
 176 #endif
 177
 178 void lcd_show_board_info(void)
 179 {
 180         ulong dram_size, nand_size;
 181 #ifndef CONFIG_SYS_NO_FLASH
 182         ulong flash_size;
 183 #endif
 184         int i;
 185         char temp[32];
 186
 187         lcd_printf ("%s\n", U_BOOT_VERSION);
 188         lcd_printf ("(C) 2008 ATMEL Corp\n");
 189         lcd_printf ("at91support@atmel.com\n");
 190         lcd_printf ("%s CPU at %s MHz\n",
 191                 ATMEL_CPU_NAME,
 192                 strmhz(temp, get_cpu_clk_rate()));
 193
 194         dram_size = 0;
 195         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 196                 dram_size += gd->bd->bi_dram[i].size;
 197         nand_size = 0;
 198         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 199                 nand_size += nand_info[i].size;
 200 #ifndef CONFIG_SYS_NO_FLASH
 201         flash_size = 0;
 202         for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 203                 flash_size += flash_info[i].size;
 204 #endif
 205         lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
 206                 dram_size >> 20,
 207                 nand_size >> 20 );
 208 #ifndef CONFIG_SYS_NO_FLASH
 209         lcd_printf (",\n  %ld MB NOR",
 210                 flash_size >> 20);
 211 #endif
 212         lcd_puts ("\n");
 213 }
 214 #endif /* CONFIG_LCD_INFO */
 215 #endif
 216
 217 int board_early_init_f(void)
 218 {
 219         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 220
 221         /* Enable clocks for all PIOs */
 222         writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
 223                 (1 << ATMEL_ID_PIOCDE),
 224                 &pmc->pcer);
 225
 226         at91_seriald_hw_init();
 227         return 0;
 228 }
 229
 230 int board_init(void)
 231 {
 232         /* arch number of AT91SAM9263EK-Board */
 233         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
 234         /* adress of boot parameters */
 235         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 236
 237 #ifdef CONFIG_CMD_NAND
 238         at91sam9263ek_nand_hw_init();
 239 #endif
 240 #ifdef CONFIG_HAS_DATAFLASH
 241         at91_set_pio_output(AT91_PIO_PORTE, 20, 1);     /* select spi0 clock */
 242         at91_spi0_hw_init(1 << 0);
 243 #endif
 244 #ifdef CONFIG_MACB
 245         at91sam9263ek_macb_hw_init();
 246 #endif
 247 #ifdef CONFIG_USB_OHCI_NEW
 248         at91_uhp_hw_init();
 249 #endif
 250 #ifdef CONFIG_LCD
 251         at91sam9263ek_lcd_hw_init();
 252 #endif
 253         return 0;
 254 }
 255
 256 int dram_init(void)
 257 {
 258         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 259                 CONFIG_SYS_SDRAM_SIZE);
 260
 261         return 0;
 262 }
 263
 264 #ifdef CONFIG_RESET_PHY_R
 265 void reset_phy(void)
 266 {
 267 }
 268 #endif
 269
 270 int board_eth_init(bd_t *bis)
 271 {
 272         int rc = 0;
 273 #ifdef CONFIG_MACB
 274         rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
 275 #endif
 276         return rc;
 277 }