2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/sizes.h>
27 #include <asm/arch/at91sam9263.h>
28 #include <asm/arch/at91sam9_smc.h>
29 #include <asm/arch/at91_common.h>
30 #include <asm/arch/at91_pmc.h>
31 #include <asm/arch/at91_rstc.h>
32 #include <asm/arch/at91_matrix.h>
33 #include <asm/arch/at91_pio.h>
34 #include <asm/arch/clk.h>
35 #include <asm/arch/io.h>
36 #include <asm/arch/hardware.h>
38 #include <atmel_lcdc.h>
39 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
44 DECLARE_GLOBAL_DATA_PTR
;
46 /* ------------------------------------------------------------------------- */
48 * Miscelaneous platform dependent initialisations
51 #ifdef CONFIG_CMD_NAND
52 static void at91sam9263ek_nand_hw_init(void)
55 at91_smc_t
*smc
= (at91_smc_t
*) AT91_SMC0_BASE
;
56 at91_matrix_t
*matrix
= (at91_matrix_t
*) AT91_MATRIX_BASE
;
57 at91_pmc_t
*pmc
= (at91_pmc_t
*) AT91_PMC_BASE
;
60 csa
= readl(&matrix
->csa
[0]) | AT91_MATRIX_CSA_EBI_CS3A
;
61 writel(csa
, &matrix
->csa
[0]);
65 /* Configure SMC CS3 for NAND/SmartMedia */
66 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
67 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
70 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
71 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
74 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
76 writel(AT91_SMC_MODE_RM_NRD
| AT91_SMC_MODE_WM_NWE
|
77 AT91_SMC_MODE_EXNW_DISABLE
|
78 #ifdef CONFIG_SYS_NAND_DBW_16
79 AT91_SMC_MODE_DBW_16
|
80 #else /* CONFIG_SYS_NAND_DBW_8 */
83 AT91_SMC_MODE_TDF_CYCLE(2),
86 writel(1 << AT91SAM9263_ID_PIOA
| 1 << AT91SAM9263_ID_PIOCDE
,
89 /* Configure RDY/BSY */
90 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN
, 1);
92 /* Enable NandFlash */
93 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN
, 1);
98 static void at91sam9263ek_macb_hw_init(void)
101 at91_pmc_t
*pmc
= (at91_pmc_t
*) AT91_PMC_BASE
;
102 at91_pio_t
*pio
= (at91_pio_t
*) AT91_PIO_BASE
;
103 at91_rstc_t
*rstc
= (at91_rstc_t
*) AT91_RSTC_BASE
;
105 writel(1 << AT91SAM9263_ID_EMAC
, &pmc
->pcer
);
108 * Disable pull-up on:
109 * RXDV (PC25) => PHY normal mode (not Test mode)
110 * ERX0 (PE25) => PHY ADDR0
111 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
113 * PHY has internal pull-down
116 writel(1 << 25, &pio
->pioc
.pudr
);
117 writel((1 << 25) | (1 <<26), &pio
->pioe
.pudr
);
119 erstl
= readl(&rstc
->mr
) & AT91_RSTC_MR_ERSTL_MASK
;
121 /* Need to reset PHY -> 500ms reset */
122 writel(AT91_RSTC_KEY
| AT91_RSTC_MR_ERSTL(0x0D) |
123 AT91_RSTC_MR_URSTEN
, &rstc
->mr
);
125 writel(AT91_RSTC_KEY
| AT91_RSTC_CR_EXTRST
, &rstc
->cr
);
126 /* Wait for end hardware reset */
127 while (!(readl(&rstc
->sr
) & AT91_RSTC_SR_NRSTL
))
130 /* Restore NRST value */
131 writel(AT91_RSTC_KEY
| erstl
| AT91_RSTC_MR_URSTEN
, &rstc
->mr
);
133 /* Re-enable pull-up */
134 writel(1 << 25, &pio
->pioc
.puer
);
135 writel((1 << 25) | (1 <<26), &pio
->pioe
.puer
);
142 vidinfo_t panel_info
= {
146 vl_sync
: ATMEL_LCDC_INVLINE_INVERTED
|
147 ATMEL_LCDC_INVFRAME_INVERTED
,
156 mmio
: AT91SAM9263_LCDC_BASE
,
159 void lcd_enable(void)
161 at91_set_pio_value(AT91_PIO_PORTA
, 30, 1); /* power up */
164 void lcd_disable(void)
166 at91_set_pio_value(AT91_PIO_PORTA
, 30, 0); /* power down */
169 static void at91sam9263ek_lcd_hw_init(void)
171 at91_pmc_t
*pmc
= (at91_pmc_t
*) AT91_PMC_BASE
;
173 at91_set_a_periph(AT91_PIO_PORTC
, 1, 0); /* LCDHSYNC */
174 at91_set_a_periph(AT91_PIO_PORTC
, 2, 0); /* LCDDOTCK */
175 at91_set_a_periph(AT91_PIO_PORTC
, 3, 0); /* LCDDEN */
176 at91_set_b_periph(AT91_PIO_PORTB
, 9, 0); /* LCDCC */
177 at91_set_a_periph(AT91_PIO_PORTC
, 6, 0); /* LCDD2 */
178 at91_set_a_periph(AT91_PIO_PORTC
, 7, 0); /* LCDD3 */
179 at91_set_a_periph(AT91_PIO_PORTC
, 8, 0); /* LCDD4 */
180 at91_set_a_periph(AT91_PIO_PORTC
, 9, 0); /* LCDD5 */
181 at91_set_a_periph(AT91_PIO_PORTC
, 10, 0); /* LCDD6 */
182 at91_set_a_periph(AT91_PIO_PORTC
, 11, 0); /* LCDD7 */
183 at91_set_a_periph(AT91_PIO_PORTC
, 14, 0); /* LCDD10 */
184 at91_set_a_periph(AT91_PIO_PORTC
, 15, 0); /* LCDD11 */
185 at91_set_a_periph(AT91_PIO_PORTC
, 16, 0); /* LCDD12 */
186 at91_set_b_periph(AT91_PIO_PORTC
, 12, 0); /* LCDD13 */
187 at91_set_a_periph(AT91_PIO_PORTC
, 18, 0); /* LCDD14 */
188 at91_set_a_periph(AT91_PIO_PORTC
, 19, 0); /* LCDD15 */
189 at91_set_a_periph(AT91_PIO_PORTC
, 22, 0); /* LCDD18 */
190 at91_set_a_periph(AT91_PIO_PORTC
, 23, 0); /* LCDD19 */
191 at91_set_a_periph(AT91_PIO_PORTC
, 24, 0); /* LCDD20 */
192 at91_set_b_periph(AT91_PIO_PORTC
, 17, 0); /* LCDD21 */
193 at91_set_a_periph(AT91_PIO_PORTC
, 26, 0); /* LCDD22 */
194 at91_set_a_periph(AT91_PIO_PORTC
, 27, 0); /* LCDD23 */
196 writel(1 << AT91SAM9263_ID_LCDC
, &pmc
->pcer
);
197 gd
->fb_base
= AT91SAM9263_SRAM0_BASE
;
200 #ifdef CONFIG_LCD_INFO
204 #ifndef CONFIG_SYS_NO_FLASH
205 extern flash_info_t flash_info
[];
208 void lcd_show_board_info(void)
210 ulong dram_size
, nand_size
;
211 #ifndef CONFIG_SYS_NO_FLASH
217 lcd_printf ("%s\n", U_BOOT_VERSION
);
218 lcd_printf ("(C) 2008 ATMEL Corp\n");
219 lcd_printf ("at91support@atmel.com\n");
220 lcd_printf ("%s CPU at %s MHz\n",
221 CONFIG_SYS_AT91_CPU_NAME
,
222 strmhz(temp
, get_cpu_clk_rate()));
225 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++)
226 dram_size
+= gd
->bd
->bi_dram
[i
].size
;
228 for (i
= 0; i
< CONFIG_SYS_MAX_NAND_DEVICE
; i
++)
229 nand_size
+= nand_info
[i
].size
;
230 #ifndef CONFIG_SYS_NO_FLASH
232 for (i
= 0; i
< CONFIG_SYS_MAX_FLASH_BANKS
; i
++)
233 flash_size
+= flash_info
[i
].size
;
235 lcd_printf (" %ld MB SDRAM, %ld MB NAND",
238 #ifndef CONFIG_SYS_NO_FLASH
239 lcd_printf (",\n %ld MB NOR",
244 #endif /* CONFIG_LCD_INFO */
252 /* arch number of AT91SAM9263EK-Board */
253 gd
->bd
->bi_arch_number
= MACH_TYPE_AT91SAM9263EK
;
254 /* adress of boot parameters */
255 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
257 at91_serial_hw_init();
258 #ifdef CONFIG_CMD_NAND
259 at91sam9263ek_nand_hw_init();
261 #ifdef CONFIG_HAS_DATAFLASH
262 at91_set_pio_output(AT91_PIO_PORTE
, 20, 1); /* select spi0 clock */
263 at91_spi0_hw_init(1 << 0);
266 at91sam9263ek_macb_hw_init();
268 #ifdef CONFIG_USB_OHCI_NEW
272 at91sam9263ek_lcd_hw_init();
279 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM
;
280 gd
->bd
->bi_dram
[0].size
= PHYS_SDRAM_SIZE
;
284 #ifdef CONFIG_RESET_PHY_R
290 int board_eth_init(bd_t
*bis
)
294 rc
= macb_eth_initialize(0, (void *) AT91_EMAC_BASE
, 0x00);