board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clk.h>
  12 #include <asm/arch/at91sam9g45_matrix.h>
  13 #include <asm/arch/at91sam9_smc.h>
  14 #include <asm/arch/at91_common.h>
  15 #include <asm/arch/at91_pmc.h>
  16 #include <asm/arch/gpio.h>
  17 #include <asm/arch/clk.h>
  18 #include <lcd.h>
  19 #include <linux/mtd/nand.h>
  20 #include <atmel_lcdc.h>
  21 #include <atmel_mci.h>
  22 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  23 #include <net.h>
  24 #endif
  25 #include <netdev.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 /* ------------------------------------------------------------------------- */
  30 /*
  31  * Miscelaneous platform dependent initialisations
  32  */
  33
  34 #ifdef CONFIG_CMD_NAND
  35 void at91sam9m10g45ek_nand_hw_init(void)
  36 {
  37         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  38         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  39         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  40         unsigned long csa;
  41
  42         /* Enable CS3 */
  43         csa = readl(&matrix->ebicsa);
  44         csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  45         writel(csa, &matrix->ebicsa);
  46
  47         /* Configure SMC CS3 for NAND/SmartMedia */
  48         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  49                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  50                &smc->cs[3].setup);
  51         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
  52                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
  53                &smc->cs[3].pulse);
  54         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
  55                &smc->cs[3].cycle);
  56         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  57                AT91_SMC_MODE_EXNW_DISABLE |
  58 #ifdef CONFIG_SYS_NAND_DBW_16
  59                AT91_SMC_MODE_DBW_16 |
  60 #else /* CONFIG_SYS_NAND_DBW_8 */
  61                AT91_SMC_MODE_DBW_8 |
  62 #endif
  63                AT91_SMC_MODE_TDF_CYCLE(3),
  64                &smc->cs[3].mode);
  65
  66         writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  67
  68         /* Configure RDY/BSY */
  69         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  70
  71         /* Enable NandFlash */
  72         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  73 }
  74 #endif
  75
  76 #if defined(CONFIG_SPL_BUILD)
  77 #include <spl.h>
  78 #include <nand.h>
  79
  80 void at91_spl_board_init(void)
  81 {
  82         /*
  83          * On the at91sam9m10g45ek board, the chip wm9711 stays in the
  84          * test mode, so it needs do some action to exit test mode.
  85          */
  86         at91_periph_clk_enable(ATMEL_ID_PIODE);
  87         at91_set_gpio_output(AT91_PIN_PD7, 0);
  88         at91_set_gpio_output(AT91_PIN_PD8, 0);
  89         at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
  90         at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
  91
  92 #ifdef CONFIG_SYS_USE_MMC
  93         at91_mci_hw_init();
  94 #elif CONFIG_SYS_USE_NANDFLASH
  95         at91sam9m10g45ek_nand_hw_init();
  96 #endif
  97 }
  98
  99 #include <asm/arch/atmel_mpddrc.h>
 100 static void ddr2_conf(struct atmel_mpddr *ddr2)
 101 {
 102         ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 103
 104         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 105                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 106                     ATMEL_MPDDRC_CR_DQMS_SHARED |
 107                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
 108
 109         ddr2->rtr = 0x24b;
 110
 111         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
 112                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
 113                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
 114                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
 115                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
 116                       1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
 117                       1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
 118                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
 119
 120         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
 121                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 122                       16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 123                       14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 124
 125         ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 126                       0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 127                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 128                       2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 129 }
 130
 131 void mem_init(void)
 132 {
 133         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 134         struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 135         struct atmel_mpddr ddr2;
 136         unsigned long csa;
 137
 138         ddr2_conf(&ddr2);
 139
 140         /* enable DDR2 clock */
 141         writel(0x4, &pmc->scer);
 142
 143         /* Chip select 1 is for DDR2/SDRAM */
 144         csa = readl(&mat->ebicsa);
 145         csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
 146         csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
 147         writel(csa, &mat->ebicsa);
 148
 149         /* DDRAM2 Controller initialize */
 150         ddr2_init(ATMEL_BASE_CS6, &ddr2);
 151 }
 152 #endif
 153
 154 #ifdef CONFIG_CMD_USB
 155 static void at91sam9m10g45ek_usb_hw_init(void)
 156 {
 157         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 158
 159         writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
 160
 161         at91_set_gpio_output(AT91_PIN_PD1, 0);
 162         at91_set_gpio_output(AT91_PIN_PD3, 0);
 163 }
 164 #endif
 165
 166 #ifdef CONFIG_MACB
 167 static void at91sam9m10g45ek_macb_hw_init(void)
 168 {
 169         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 170         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
 171
 172         /* Enable clock */
 173         writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 174
 175         /*
 176          * Disable pull-up on:
 177          *      RXDV (PA15) => PHY normal mode (not Test mode)
 178          *      ERX0 (PA12) => PHY ADDR0
 179          *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
 180          *
 181          * PHY has internal pull-down
 182          */
 183         writel(pin_to_mask(AT91_PIN_PA15) |
 184                pin_to_mask(AT91_PIN_PA12) |
 185                pin_to_mask(AT91_PIN_PA13),
 186                &pioa->pudr);
 187
 188         at91_phy_reset();
 189
 190         /* Re-enable pull-up */
 191         writel(pin_to_mask(AT91_PIN_PA15) |
 192                pin_to_mask(AT91_PIN_PA12) |
 193                pin_to_mask(AT91_PIN_PA13),
 194                &pioa->puer);
 195
 196         /* And the pins. */
 197         at91_macb_hw_init();
 198 }
 199 #endif
 200
 201 #ifdef CONFIG_LCD
 202
 203 vidinfo_t panel_info = {
 204         .vl_col =               480,
 205         .vl_row =               272,
 206         .vl_clk =               9000000,
 207         .vl_sync =              ATMEL_LCDC_INVLINE_NORMAL |
 208                                 ATMEL_LCDC_INVFRAME_NORMAL,
 209         .vl_bpix =              3,
 210         .vl_tft =               1,
 211         .vl_hsync_len =         45,
 212         .vl_left_margin =       1,
 213         .vl_right_margin =      1,
 214         .vl_vsync_len =         1,
 215         .vl_upper_margin =      40,
 216         .vl_lower_margin =      1,
 217         .mmio =                 ATMEL_BASE_LCDC,
 218 };
 219
 220
 221 void lcd_enable(void)
 222 {
 223         at91_set_A_periph(AT91_PIN_PE6, 1);     /* power up */
 224 }
 225
 226 void lcd_disable(void)
 227 {
 228         at91_set_A_periph(AT91_PIN_PE6, 0);     /* power down */
 229 }
 230
 231 static void at91sam9m10g45ek_lcd_hw_init(void)
 232 {
 233         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 234
 235         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 236         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
 237         at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
 238         at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
 239         at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
 240
 241         at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
 242         at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
 243         at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
 244         at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
 245         at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
 246         at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
 247         at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
 248         at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
 249         at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
 250         at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
 251         at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
 252         at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
 253         at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
 254         at91_set_B_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
 255         at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
 256         at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
 257         at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
 258         at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
 259         at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
 260         at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
 261         at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
 262         at91_set_B_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
 263         at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
 264         at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
 265
 266         writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
 267
 268         gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
 269 }
 270
 271 #ifdef CONFIG_LCD_INFO
 272 #include <nand.h>
 273 #include <version.h>
 274
 275 void lcd_show_board_info(void)
 276 {
 277         ulong dram_size, nand_size;
 278         int i;
 279         char temp[32];
 280
 281         lcd_printf ("%s\n", U_BOOT_VERSION);
 282         lcd_printf ("(C) 2008 ATMEL Corp\n");
 283         lcd_printf ("at91support@atmel.com\n");
 284         lcd_printf ("%s CPU at %s MHz\n",
 285                 ATMEL_CPU_NAME,
 286                 strmhz(temp, get_cpu_clk_rate()));
 287
 288         dram_size = 0;
 289         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 290                 dram_size += gd->bd->bi_dram[i].size;
 291         nand_size = 0;
 292         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 293                 nand_size += nand_info[i].size;
 294         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 295                 dram_size >> 20,
 296                 nand_size >> 20 );
 297 }
 298 #endif /* CONFIG_LCD_INFO */
 299 #endif
 300
 301 #ifdef CONFIG_GENERIC_ATMEL_MCI
 302 int board_mmc_init(bd_t *bis)
 303 {
 304         at91_mci_hw_init();
 305
 306         return atmel_mci_init((void *)ATMEL_BASE_MCI0);
 307 }
 308 #endif
 309
 310 int board_early_init_f(void)
 311 {
 312         at91_seriald_hw_init();
 313         return 0;
 314 }
 315
 316 int board_init(void)
 317 {
 318         /* arch number of AT91SAM9M10G45EK-Board */
 319 #ifdef CONFIG_AT91SAM9M10G45EK
 320         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
 321 #elif defined CONFIG_AT91SAM9G45EKES
 322         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
 323 #endif
 324
 325         /* adress of boot parameters */
 326         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 327
 328 #ifdef CONFIG_CMD_NAND
 329         at91sam9m10g45ek_nand_hw_init();
 330 #endif
 331 #ifdef CONFIG_CMD_USB
 332         at91sam9m10g45ek_usb_hw_init();
 333 #endif
 334 #ifdef CONFIG_HAS_DATAFLASH
 335         at91_spi0_hw_init(1 << 0);
 336 #endif
 337 #ifdef CONFIG_ATMEL_SPI
 338         at91_spi0_hw_init(1 << 4);
 339 #endif
 340 #ifdef CONFIG_MACB
 341         at91sam9m10g45ek_macb_hw_init();
 342 #endif
 343 #ifdef CONFIG_LCD
 344         at91sam9m10g45ek_lcd_hw_init();
 345 #endif
 346         return 0;
 347 }
 348
 349 int dram_init(void)
 350 {
 351         gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
 352                                     CONFIG_SYS_SDRAM_SIZE);
 353         return 0;
 354 }
 355
 356 #ifdef CONFIG_RESET_PHY_R
 357 void reset_phy(void)
 358 {
 359 }
 360 #endif
 361
 362 int board_eth_init(bd_t *bis)
 363 {
 364         int rc = 0;
 365 #ifdef CONFIG_MACB
 366         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 367 #endif
 368         return rc;
 369 }
 370
 371 /* SPI chip select control */
 372 #ifdef CONFIG_ATMEL_SPI
 373 #include <spi.h>
 374
 375 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 376 {
 377         return bus == 0 && cs < 2;
 378 }
 379
 380 void spi_cs_activate(struct spi_slave *slave)
 381 {
 382         switch(slave->cs) {
 383                 case 1:
 384                         at91_set_gpio_output(AT91_PIN_PB18, 0);
 385                         break;
 386                 case 0:
 387                 default:
 388                         at91_set_gpio_output(AT91_PIN_PB3, 0);
 389                         break;
 390         }
 391 }
 392
 393 void spi_cs_deactivate(struct spi_slave *slave)
 394 {
 395         switch(slave->cs) {
 396                 case 1:
 397                         at91_set_gpio_output(AT91_PIN_PB18, 1);
 398                         break;
 399                 case 0:
 400                 default:
 401                         at91_set_gpio_output(AT91_PIN_PB3, 1);
 402                 break;
 403         }
 404 }
 405 #endif /* CONFIG_ATMEL_SPI */