2 * (C) Copyright 2013 Atmel Corporation
3 * Josh Wu <josh.wu@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/at91sam9x5_matrix.h>
11 #include <asm/arch/at91sam9_smc.h>
12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/at91_rstc.h>
14 #include <asm/arch/at91_pio.h>
15 #include <asm/arch/clk.h>
16 #include <debug_uart.h>
18 #include <atmel_hlcdc.h>
21 #ifdef CONFIG_LCD_INFO
26 DECLARE_GLOBAL_DATA_PTR
;
28 /* ------------------------------------------------------------------------- */
30 * Miscelaneous platform dependent initialisations
32 #ifdef CONFIG_NAND_ATMEL
33 static void at91sam9n12ek_nand_hw_init(void)
35 struct at91_smc
*smc
= (struct at91_smc
*)ATMEL_BASE_SMC
;
36 struct at91_matrix
*matrix
= (struct at91_matrix
*)ATMEL_BASE_MATRIX
;
39 /* Assign CS3 to NAND/SmartMedia Interface */
40 csa
= readl(&matrix
->ebicsa
);
41 csa
|= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA
;
42 /* Configure databus */
43 csa
&= ~AT91_MATRIX_NFD0_ON_D16
; /* nandflash connect to D0~D15 */
44 /* Configure IO drive */
45 csa
|= AT91_MATRIX_EBI_EBI_IOSR_NORMAL
;
47 writel(csa
, &matrix
->ebicsa
);
49 /* Configure SMC CS3 for NAND/SmartMedia */
50 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
51 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
53 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
54 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
56 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
58 writel(AT91_SMC_MODE_RM_NRD
| AT91_SMC_MODE_WM_NWE
|
59 AT91_SMC_MODE_EXNW_DISABLE
|
60 #ifdef CONFIG_SYS_NAND_DBW_16
61 AT91_SMC_MODE_DBW_16
|
62 #else /* CONFIG_SYS_NAND_DBW_8 */
65 AT91_SMC_MODE_TDF_CYCLE(1),
68 /* Configure RDY/BSY pin */
69 at91_set_pio_input(AT91_PIO_PORTD
, 5, 1);
71 /* Configure ENABLE pin for NandFlash */
72 at91_set_pio_output(AT91_PIO_PORTD
, 4, 1);
74 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 0, 1); /* NAND OE */
75 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 1, 1); /* NAND WE */
76 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 2, 1); /* ALE */
77 at91_pio3_set_a_periph(AT91_PIO_PORTD
, 3, 1); /* CLE */
82 vidinfo_t panel_info
= {
91 .vl_right_margin
= 43,
94 .vl_lower_margin
= 12,
95 .mmio
= ATMEL_BASE_LCDC
,
100 at91_set_pio_output(AT91_PIO_PORTC
, 25, 0); /* power up */
103 void lcd_disable(void)
105 at91_set_pio_output(AT91_PIO_PORTC
, 25, 1); /* power down */
108 #ifdef CONFIG_LCD_INFO
109 void lcd_show_board_info(void)
111 ulong dram_size
, nand_size
;
115 lcd_printf("%s\n", U_BOOT_VERSION
);
116 lcd_printf("ATMEL Corp\n");
117 lcd_printf("at91@atmel.com\n");
118 lcd_printf("%s CPU at %s MHz\n",
120 strmhz(temp
, get_cpu_clk_rate()));
123 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++)
124 dram_size
+= gd
->bd
->bi_dram
[i
].size
;
126 for (i
= 0; i
< CONFIG_SYS_MAX_NAND_DEVICE
; i
++)
127 nand_size
+= nand_info
[i
]->size
;
128 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
132 #endif /* CONFIG_LCD_INFO */
133 #endif /* CONFIG_LCD */
135 #ifdef CONFIG_KS8851_MLL
136 void at91sam9n12ek_ks8851_hw_init(void)
138 struct at91_smc
*smc
= (struct at91_smc
*)ATMEL_BASE_SMC
;
140 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
141 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
143 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
144 AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
146 writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
148 writel(AT91_SMC_MODE_RM_NRD
| AT91_SMC_MODE_WM_NWE
|
149 AT91_SMC_MODE_EXNW_DISABLE
|
150 AT91_SMC_MODE_BAT
| AT91_SMC_MODE_DBW_16
|
151 AT91_SMC_MODE_TDF_CYCLE(1),
154 /* Configure NCS2 PIN */
155 at91_pio3_set_b_periph(AT91_PIO_PORTD
, 19, 0);
159 #ifdef CONFIG_USB_ATMEL
160 void at91sam9n12ek_usb_hw_init(void)
162 at91_set_pio_output(AT91_PIO_PORTB
, 7, 0);
166 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
167 void board_debug_uart_init(void)
169 at91_seriald_hw_init();
173 #ifdef CONFIG_BOARD_EARLY_INIT_F
174 int board_early_init_f(void)
176 #ifdef CONFIG_DEBUG_UART
185 /* adress of boot parameters */
186 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
188 #ifdef CONFIG_NAND_ATMEL
189 at91sam9n12ek_nand_hw_init();
196 #ifdef CONFIG_KS8851_MLL
197 at91sam9n12ek_ks8851_hw_init();
200 #ifdef CONFIG_USB_ATMEL
201 at91sam9n12ek_usb_hw_init();
207 #ifdef CONFIG_KS8851_MLL
208 int board_eth_init(bd_t
*bis
)
210 return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR
);
216 gd
->ram_size
= get_ram_size((void *)CONFIG_SYS_SDRAM_BASE
,
217 CONFIG_SYS_SDRAM_SIZE
);
221 #if defined(CONFIG_SPL_BUILD)
225 void at91_spl_board_init(void)
227 #ifdef CONFIG_SYS_USE_MMC
229 #elif CONFIG_SYS_USE_NANDFLASH
230 at91sam9n12ek_nand_hw_init();
231 #elif CONFIG_SYS_USE_SPIFLASH
232 at91_spi0_hw_init(1 << 4);
236 #include <asm/arch/atmel_mpddrc.h>
237 static void ddr2_conf(struct atmel_mpddrc_config
*ddr2
)
239 ddr2
->md
= (ATMEL_MPDDRC_MD_DBW_16_BITS
| ATMEL_MPDDRC_MD_DDR2_SDRAM
);
241 ddr2
->cr
= (ATMEL_MPDDRC_CR_NC_COL_10
|
242 ATMEL_MPDDRC_CR_NR_ROW_13
|
243 ATMEL_MPDDRC_CR_CAS_DDR_CAS3
|
244 ATMEL_MPDDRC_CR_NB_8BANKS
|
245 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
);
249 ddr2
->tpr0
= (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET
|
250 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET
|
251 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET
|
252 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET
|
253 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET
|
254 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET
|
255 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET
|
256 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET
);
258 ddr2
->tpr1
= (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET
|
259 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET
|
260 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET
|
261 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET
);
263 ddr2
->tpr2
= (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET
|
264 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET
|
265 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET
|
266 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET
);
271 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
272 struct at91_matrix
*matrix
= (struct at91_matrix
*)ATMEL_BASE_MATRIX
;
273 struct atmel_mpddrc_config ddr2
;
278 /* enable DDR2 clock */
279 writel(AT91_PMC_DDR
, &pmc
->scer
);
281 /* Chip select 1 is for DDR2/SDRAM */
282 csa
= readl(&matrix
->ebicsa
);
283 csa
|= AT91_MATRIX_EBI_CS1A_SDRAMC
;
284 csa
&= ~AT91_MATRIX_EBI_DBPU_OFF
;
285 csa
|= AT91_MATRIX_EBI_DBPD_OFF
;
286 csa
|= AT91_MATRIX_EBI_EBI_IOSR_NORMAL
;
287 writel(csa
, &matrix
->ebicsa
);
289 /* DDRAM2 Controller initialize */
290 ddr2_init(ATMEL_BASE_DDRSDRC
, ATMEL_BASE_CS1
, &ddr2
);