board/atmel/at91sam9n12ek/at91sam9n12ek.c

   1 /*
   2  * (C) Copyright 2013 Atmel Corporation
   3  * Josh Wu <josh.wu@atmel.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/at91sam9x5_matrix.h>
  11 #include <asm/arch/at91sam9_smc.h>
  12 #include <asm/arch/at91_common.h>
  13 #include <asm/arch/at91_pmc.h>
  14 #include <asm/arch/at91_rstc.h>
  15 #include <asm/arch/at91_pio.h>
  16 #include <asm/arch/clk.h>
  17 #include <lcd.h>
  18 #include <atmel_hlcdc.h>
  19 #include <atmel_mci.h>
  20 #include <netdev.h>
  21
  22 #ifdef CONFIG_LCD_INFO
  23 #include <nand.h>
  24 #include <version.h>
  25 #endif
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 /* ------------------------------------------------------------------------- */
  30 /*
  31  * Miscelaneous platform dependent initialisations
  32  */
  33 #ifdef CONFIG_NAND_ATMEL
  34 static void at91sam9n12ek_nand_hw_init(void)
  35 {
  36         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  37         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  38         unsigned long csa;
  39
  40         /* Assign CS3 to NAND/SmartMedia Interface */
  41         csa = readl(&matrix->ebicsa);
  42         csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  43         /* Configure databus */
  44         csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
  45         /* Configure IO drive */
  46         csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  47
  48         writel(csa, &matrix->ebicsa);
  49
  50         /* Configure SMC CS3 for NAND/SmartMedia */
  51         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  52                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  53                 &smc->cs[3].setup);
  54         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  55                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
  56                 &smc->cs[3].pulse);
  57         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
  58                 &smc->cs[3].cycle);
  59         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  60                 AT91_SMC_MODE_EXNW_DISABLE |
  61 #ifdef CONFIG_SYS_NAND_DBW_16
  62                 AT91_SMC_MODE_DBW_16 |
  63 #else /* CONFIG_SYS_NAND_DBW_8 */
  64                 AT91_SMC_MODE_DBW_8 |
  65 #endif
  66                 AT91_SMC_MODE_TDF_CYCLE(1),
  67                 &smc->cs[3].mode);
  68
  69         /* Configure RDY/BSY pin */
  70         at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
  71
  72         /* Configure ENABLE pin for NandFlash */
  73         at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
  74
  75         at91_set_a_periph(AT91_PIO_PORTD, 0, 1);    /* NAND OE */
  76         at91_set_a_periph(AT91_PIO_PORTD, 1, 1);    /* NAND WE */
  77         at91_set_a_periph(AT91_PIO_PORTD, 2, 1);    /* ALE */
  78         at91_set_a_periph(AT91_PIO_PORTD, 3, 1);    /* CLE */
  79 }
  80 #endif
  81
  82 #ifdef CONFIG_LCD
  83 vidinfo_t panel_info = {
  84         .vl_col = 480,
  85         .vl_row = 272,
  86         .vl_clk = 9000000,
  87         .vl_bpix = LCD_BPP,
  88         .vl_sync = 0,
  89         .vl_tft = 1,
  90         .vl_hsync_len = 5,
  91         .vl_left_margin = 8,
  92         .vl_right_margin = 43,
  93         .vl_vsync_len = 10,
  94         .vl_upper_margin = 4,
  95         .vl_lower_margin = 12,
  96         .mmio = ATMEL_BASE_LCDC,
  97 };
  98
  99 void lcd_enable(void)
 100 {
 101         at91_set_pio_output(AT91_PIO_PORTC, 25, 0);     /* power up */
 102 }
 103
 104 void lcd_disable(void)
 105 {
 106         at91_set_pio_output(AT91_PIO_PORTC, 25, 1);     /* power down */
 107 }
 108
 109 #ifdef CONFIG_LCD_INFO
 110 void lcd_show_board_info(void)
 111 {
 112         ulong dram_size, nand_size;
 113         int i;
 114         char temp[32];
 115
 116         lcd_printf("%s\n", U_BOOT_VERSION);
 117         lcd_printf("ATMEL Corp\n");
 118         lcd_printf("at91@atmel.com\n");
 119         lcd_printf("%s CPU at %s MHz\n",
 120                 ATMEL_CPU_NAME,
 121                 strmhz(temp, get_cpu_clk_rate()));
 122
 123         dram_size = 0;
 124         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 125                 dram_size += gd->bd->bi_dram[i].size;
 126         nand_size = 0;
 127         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 128                 nand_size += nand_info[i].size;
 129         lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 130                 dram_size >> 20,
 131                 nand_size >> 20);
 132 }
 133 #endif /* CONFIG_LCD_INFO */
 134 #endif /* CONFIG_LCD */
 135
 136 /* SPI chip select control */
 137 #ifdef CONFIG_ATMEL_SPI
 138 #include <spi.h>
 139 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 140 {
 141         return bus == 0 && cs < 2;
 142 }
 143
 144 void spi_cs_activate(struct spi_slave *slave)
 145 {
 146         switch (slave->cs) {
 147         case 0:
 148                 at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
 149                 break;
 150         case 1:
 151                 at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
 152                 break;
 153         }
 154 }
 155
 156 void spi_cs_deactivate(struct spi_slave *slave)
 157 {
 158         switch (slave->cs) {
 159         case 0:
 160                 at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
 161                 break;
 162         case 1:
 163                 at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
 164                 break;
 165         }
 166 }
 167 #endif /* CONFIG_ATMEL_SPI */
 168
 169 #ifdef CONFIG_GENERIC_ATMEL_MCI
 170 int board_mmc_init(bd_t *bd)
 171 {
 172         at91_mci_hw_init();
 173
 174         return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
 175 }
 176 #endif
 177
 178 #ifdef CONFIG_KS8851_MLL
 179 void at91sam9n12ek_ks8851_hw_init(void)
 180 {
 181         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 182
 183         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
 184                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
 185                &smc->cs[2].setup);
 186         writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
 187                AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
 188                &smc->cs[2].pulse);
 189         writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
 190                &smc->cs[2].cycle);
 191         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 192                AT91_SMC_MODE_EXNW_DISABLE |
 193                AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
 194                AT91_SMC_MODE_TDF_CYCLE(1),
 195                &smc->cs[2].mode);
 196
 197         /* Configure NCS2 PIN */
 198         at91_set_b_periph(AT91_PIO_PORTD, 19, 0);
 199 }
 200 #endif
 201
 202 #ifdef CONFIG_USB_ATMEL
 203 void at91sam9n12ek_usb_hw_init(void)
 204 {
 205         at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
 206 }
 207 #endif
 208
 209 int board_early_init_f(void)
 210 {
 211         /* Enable clocks for all PIOs */
 212         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 213         writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer);
 214
 215         at91_seriald_hw_init();
 216         return 0;
 217 }
 218
 219 int board_init(void)
 220 {
 221         /* adress of boot parameters */
 222         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 223
 224 #ifdef CONFIG_NAND_ATMEL
 225         at91sam9n12ek_nand_hw_init();
 226 #endif
 227
 228 #ifdef CONFIG_ATMEL_SPI
 229         at91_spi0_hw_init(1 << 0);
 230 #endif
 231
 232 #ifdef CONFIG_LCD
 233         at91_lcd_hw_init();
 234 #endif
 235
 236 #ifdef CONFIG_KS8851_MLL
 237         at91sam9n12ek_ks8851_hw_init();
 238 #endif
 239
 240 #ifdef CONFIG_USB_ATMEL
 241         at91sam9n12ek_usb_hw_init();
 242 #endif
 243
 244         return 0;
 245 }
 246
 247 #ifdef CONFIG_KS8851_MLL
 248 int board_eth_init(bd_t *bis)
 249 {
 250         return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
 251 }
 252 #endif
 253
 254 int dram_init(void)
 255 {
 256         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 257                                         CONFIG_SYS_SDRAM_SIZE);
 258         return 0;
 259 }
 260
 261 #if defined(CONFIG_SPL_BUILD)
 262 #include <spl.h>
 263 #include <nand.h>
 264
 265 void at91_spl_board_init(void)
 266 {
 267 #ifdef CONFIG_SYS_USE_MMC
 268         at91_mci_hw_init();
 269 #elif CONFIG_SYS_USE_NANDFLASH
 270         at91sam9n12ek_nand_hw_init();
 271 #elif CONFIG_SYS_USE_SPIFLASH
 272         at91_spi0_hw_init(1 << 4);
 273 #endif
 274 }
 275
 276 #include <asm/arch/atmel_mpddrc.h>
 277 static void ddr2_conf(struct atmel_mpddr *ddr2)
 278 {
 279         ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 280
 281         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 282                     ATMEL_MPDDRC_CR_NR_ROW_13 |
 283                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 284                     ATMEL_MPDDRC_CR_NB_8BANKS |
 285                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
 286
 287         ddr2->rtr = 0x411;
 288
 289         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 290                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 291                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 292                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 293                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 294                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 295                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 296                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 297
 298         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 299                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 300                       19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 301                       18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 302
 303         ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 304                       3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 305                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 306                       2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 307 }
 308
 309 void mem_init(void)
 310 {
 311         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 312         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 313         struct atmel_mpddr ddr2;
 314         unsigned long csa;
 315
 316         ddr2_conf(&ddr2);
 317
 318         /* enable DDR2 clock */
 319         writel(0x4, &pmc->scer);
 320
 321         /* Chip select 1 is for DDR2/SDRAM */
 322         csa = readl(&matrix->ebicsa);
 323         csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
 324         csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
 325         csa |= AT91_MATRIX_EBI_DBPD_OFF;
 326         csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
 327         writel(csa, &matrix->ebicsa);
 328
 329         /* DDRAM2 Controller initialize */
 330         ddr2_init(ATMEL_BASE_CS1, &ddr2);
 331 }
 332 #endif