2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/at91sam9rl.h>
27 #include <asm/arch/at91sam9rl_matrix.h>
28 #include <asm/arch/at91sam9_smc.h>
29 #include <asm/arch/at91_common.h>
30 #include <asm/arch/at91_pmc.h>
31 #include <asm/arch/at91_rstc.h>
32 #include <asm/arch/clk.h>
33 #include <asm/arch/gpio.h>
34 #include <asm/arch/io.h>
36 #include <atmel_lcdc.h>
37 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
41 DECLARE_GLOBAL_DATA_PTR
;
43 /* ------------------------------------------------------------------------- */
45 * Miscelaneous platform dependent initialisations
48 #ifdef CONFIG_CMD_NAND
49 static void at91sam9rlek_nand_hw_init(void)
54 csa
= at91_sys_read(AT91_MATRIX_EBICSA
);
55 at91_sys_write(AT91_MATRIX_EBICSA
,
56 csa
| AT91_MATRIX_CS3A_SMC_SMARTMEDIA
);
58 /* Configure SMC CS3 for NAND/SmartMedia */
59 at91_sys_write(AT91_SMC_SETUP(3),
60 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
61 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
62 at91_sys_write(AT91_SMC_PULSE(3),
63 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
64 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
65 at91_sys_write(AT91_SMC_CYCLE(3),
66 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
67 at91_sys_write(AT91_SMC_MODE(3),
68 AT91_SMC_READMODE
| AT91_SMC_WRITEMODE
|
69 AT91_SMC_EXNWMODE_DISABLE
|
70 #ifdef CONFIG_SYS_NAND_DBW_16
72 #else /* CONFIG_SYS_NAND_DBW_8 */
77 at91_sys_write(AT91_PMC_PCER
, 1 << AT91SAM9RL_ID_PIOD
);
79 /* Configure RDY/BSY */
80 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN
, 1);
82 /* Enable NandFlash */
83 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN
, 1);
85 at91_set_A_periph(AT91_PIN_PB4
, 0); /* NANDOE */
86 at91_set_A_periph(AT91_PIN_PB5
, 0); /* NANDWE */
91 vidinfo_t panel_info
= {
95 vl_sync
: ATMEL_LCDC_INVLINE_INVERTED
|
96 ATMEL_LCDC_INVFRAME_INVERTED
,
105 mmio
: AT91SAM9RL_LCDC_BASE
,
108 void lcd_enable(void)
110 at91_set_gpio_value(AT91_PIN_PA30
, 0); /* power up */
113 void lcd_disable(void)
115 at91_set_gpio_value(AT91_PIN_PA30
, 1); /* power down */
117 static void at91sam9rlek_lcd_hw_init(void)
119 at91_set_B_periph(AT91_PIN_PC1
, 0); /* LCDPWR */
120 at91_set_A_periph(AT91_PIN_PC5
, 0); /* LCDHSYNC */
121 at91_set_A_periph(AT91_PIN_PC6
, 0); /* LCDDOTCK */
122 at91_set_A_periph(AT91_PIN_PC7
, 0); /* LCDDEN */
123 at91_set_A_periph(AT91_PIN_PC3
, 0); /* LCDCC */
124 at91_set_B_periph(AT91_PIN_PC9
, 0); /* LCDD3 */
125 at91_set_B_periph(AT91_PIN_PC10
, 0); /* LCDD4 */
126 at91_set_B_periph(AT91_PIN_PC11
, 0); /* LCDD5 */
127 at91_set_B_periph(AT91_PIN_PC12
, 0); /* LCDD6 */
128 at91_set_B_periph(AT91_PIN_PC13
, 0); /* LCDD7 */
129 at91_set_B_periph(AT91_PIN_PC15
, 0); /* LCDD11 */
130 at91_set_B_periph(AT91_PIN_PC16
, 0); /* LCDD12 */
131 at91_set_B_periph(AT91_PIN_PC17
, 0); /* LCDD13 */
132 at91_set_B_periph(AT91_PIN_PC18
, 0); /* LCDD14 */
133 at91_set_B_periph(AT91_PIN_PC19
, 0); /* LCDD15 */
134 at91_set_B_periph(AT91_PIN_PC20
, 0); /* LCDD18 */
135 at91_set_B_periph(AT91_PIN_PC21
, 0); /* LCDD19 */
136 at91_set_B_periph(AT91_PIN_PC22
, 0); /* LCDD20 */
137 at91_set_B_periph(AT91_PIN_PC23
, 0); /* LCDD21 */
138 at91_set_B_periph(AT91_PIN_PC24
, 0); /* LCDD22 */
139 at91_set_B_periph(AT91_PIN_PC25
, 0); /* LCDD23 */
141 at91_sys_write(AT91_PMC_PCER
, 1 << AT91SAM9RL_ID_LCDC
);
146 #ifdef CONFIG_LCD_INFO
150 void lcd_show_board_info(void)
152 ulong dram_size
, nand_size
;
156 lcd_printf ("%s\n", U_BOOT_VERSION
);
157 lcd_printf ("(C) 2008 ATMEL Corp\n");
158 lcd_printf ("at91support@atmel.com\n");
159 lcd_printf ("%s CPU at %s MHz\n",
161 strmhz(temp
, get_cpu_clk_rate()));
164 for (i
= 0; i
< CONFIG_NR_DRAM_BANKS
; i
++)
165 dram_size
+= gd
->bd
->bi_dram
[i
].size
;
167 for (i
= 0; i
< CONFIG_SYS_MAX_NAND_DEVICE
; i
++)
168 nand_size
+= nand_info
[i
].size
;
169 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
173 #endif /* CONFIG_LCD_INFO */
182 /* arch number of AT91SAM9RLEK-Board */
183 gd
->bd
->bi_arch_number
= MACH_TYPE_AT91SAM9RLEK
;
184 /* adress of boot parameters */
185 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
187 at91_serial_hw_init();
188 #ifdef CONFIG_CMD_NAND
189 at91sam9rlek_nand_hw_init();
191 #ifdef CONFIG_HAS_DATAFLASH
192 at91_spi0_hw_init(1 << 0);
195 at91sam9rlek_lcd_hw_init();
202 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM
;
203 gd
->bd
->bi_dram
[0].size
= PHYS_SDRAM_SIZE
;