board/atmel/at91sam9rlek/at91sam9rlek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/arch/at91sam9rl.h>
  27 #include <asm/arch/at91sam9rl_matrix.h>
  28 #include <asm/arch/at91sam9_smc.h>
  29 #include <asm/arch/at91_pmc.h>
  30 #include <asm/arch/at91_rstc.h>
  31 #include <asm/arch/gpio.h>
  32 #include <asm/arch/io.h>
  33 #include <lcd.h>
  34 #include <atmel_lcdc.h>
  35 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  36 #include <net.h>
  37 #endif
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 /* ------------------------------------------------------------------------- */
  42 /*
  43  * Miscelaneous platform dependent initialisations
  44  */
  45
  46 static void at91sam9rlek_serial_hw_init(void)
  47 {
  48 #ifdef CONFIG_USART0
  49         at91_set_A_periph(AT91_PIN_PA6, 1);             /* TXD0 */
  50         at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
  51         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
  52 #endif
  53
  54 #ifdef CONFIG_USART1
  55         at91_set_A_periph(AT91_PIN_PA11, 1);            /* TXD1 */
  56         at91_set_A_periph(AT91_PIN_PA12, 0);            /* RXD1 */
  57         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
  58 #endif
  59
  60 #ifdef CONFIG_USART2
  61         at91_set_A_periph(AT91_PIN_PA13, 1);            /* TXD2 */
  62         at91_set_A_periph(AT91_PIN_PA14, 0);            /* RXD2 */
  63         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
  64 #endif
  65
  66 #ifdef CONFIG_USART3    /* DBGU */
  67         at91_set_A_periph(AT91_PIN_PA21, 0);            /* DRXD */
  68         at91_set_A_periph(AT91_PIN_PA22, 1);            /* DTXD */
  69         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
  70 #endif
  71 }
  72
  73 #ifdef CONFIG_CMD_NAND
  74 static void at91sam9rlek_nand_hw_init(void)
  75 {
  76         unsigned long csa;
  77
  78         /* Enable CS3 */
  79         csa = at91_sys_read(AT91_MATRIX_EBICSA);
  80         at91_sys_write(AT91_MATRIX_EBICSA,
  81                        csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  82
  83         /* Configure SMC CS3 for NAND/SmartMedia */
  84         at91_sys_write(AT91_SMC_SETUP(3),
  85                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  86                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  87         at91_sys_write(AT91_SMC_PULSE(3),
  88                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  89                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  90         at91_sys_write(AT91_SMC_CYCLE(3),
  91                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  92         at91_sys_write(AT91_SMC_MODE(3),
  93                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  94                        AT91_SMC_EXNWMODE_DISABLE |
  95 #ifdef CONFIG_SYS_NAND_DBW_16
  96                        AT91_SMC_DBW_16 |
  97 #else /* CONFIG_SYS_NAND_DBW_8 */
  98                        AT91_SMC_DBW_8 |
  99 #endif
 100                        AT91_SMC_TDF_(2));
 101
 102         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
 103
 104         /* Configure RDY/BSY */
 105         at91_set_gpio_input(AT91_PIN_PD17, 1);
 106
 107         /* Enable NandFlash */
 108         at91_set_gpio_output(AT91_PIN_PB6, 1);
 109
 110         at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
 111         at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
 112 }
 113 #endif
 114
 115 #ifdef CONFIG_HAS_DATAFLASH
 116 static void at91sam9rlek_spi_hw_init(void)
 117 {
 118         at91_set_A_periph(AT91_PIN_PA28, 0);    /* SPI0_NPCS0 */
 119
 120         at91_set_A_periph(AT91_PIN_PA25, 0);    /* SPI0_MISO */
 121         at91_set_A_periph(AT91_PIN_PA26, 0);    /* SPI0_MOSI */
 122         at91_set_A_periph(AT91_PIN_PA27, 0);    /* SPI0_SPCK */
 123
 124         /* Enable clock */
 125         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
 126 }
 127 #endif
 128
 129 #ifdef CONFIG_LCD
 130 vidinfo_t panel_info = {
 131         vl_col:         240,
 132         vl_row:         320,
 133         vl_clk:         4965000,
 134         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 135                         ATMEL_LCDC_INVFRAME_INVERTED,
 136         vl_bpix:        3,
 137         vl_tft:         1,
 138         vl_hsync_len:   5,
 139         vl_left_margin: 1,
 140         vl_right_margin:33,
 141         vl_vsync_len:   1,
 142         vl_upper_margin:1,
 143         vl_lower_margin:0,
 144         mmio:           AT91SAM9RL_LCDC_BASE,
 145 };
 146
 147 void lcd_enable(void)
 148 {
 149         at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
 150 }
 151
 152 void lcd_disable(void)
 153 {
 154         at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
 155 }
 156 static void at91sam9rlek_lcd_hw_init(void)
 157 {
 158         at91_set_B_periph(AT91_PIN_PC1, 0);     /* LCDPWR */
 159         at91_set_A_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
 160         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
 161         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
 162         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDCC */
 163         at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
 164         at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
 165         at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
 166         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
 167         at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
 168         at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 169         at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 170         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
 171         at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 172         at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 173         at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
 174         at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
 175         at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
 176         at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
 177         at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
 178         at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
 179
 180         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_LCDC);
 181
 182         gd->fb_base = 0;
 183 }
 184 #endif
 185
 186
 187 int board_init(void)
 188 {
 189         /* Enable Ctrlc */
 190         console_init_f();
 191
 192         /* arch number of AT91SAM9RLEK-Board */
 193         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
 194         /* adress of boot parameters */
 195         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 196
 197         at91sam9rlek_serial_hw_init();
 198 #ifdef CONFIG_CMD_NAND
 199         at91sam9rlek_nand_hw_init();
 200 #endif
 201 #ifdef CONFIG_HAS_DATAFLASH
 202         at91sam9rlek_spi_hw_init();
 203 #endif
 204 #ifdef CONFIG_LCD
 205         at91sam9rlek_lcd_hw_init();
 206 #endif
 207         return 0;
 208 }
 209
 210 int dram_init(void)
 211 {
 212         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 213         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 214         return 0;
 215 }