2 * Copyright (C) 2015 Atmel Corporation
3 * Wenyou.Yang <wenyou.yang@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <debug_uart.h>
11 #include <asm/arch/at91_common.h>
12 #include <asm/arch/atmel_pio4.h>
13 #include <asm/arch/atmel_mpddrc.h>
14 #include <asm/arch/atmel_sdhci.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/sama5d2.h>
19 DECLARE_GLOBAL_DATA_PTR
;
21 static void board_usb_hw_init(void)
23 atmel_pio4_set_pio_output(AT91_PIO_PORTB
, 10, 1);
26 #ifdef CONFIG_BOARD_LATE_INIT
27 int board_late_init(void)
29 #ifdef CONFIG_DM_VIDEO
30 at91_video_show_board_info();
36 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
37 static void board_uart1_hw_init(void)
39 atmel_pio4_set_a_periph(AT91_PIO_PORTD
, 2, 1); /* URXD1 */
40 atmel_pio4_set_a_periph(AT91_PIO_PORTD
, 3, 0); /* UTXD1 */
42 at91_periph_clk_enable(ATMEL_ID_UART1
);
45 void board_debug_uart_init(void)
47 board_uart1_hw_init();
51 #ifdef CONFIG_BOARD_EARLY_INIT_F
52 int board_early_init_f(void)
54 #ifdef CONFIG_DEBUG_UART
64 /* address of boot parameters */
65 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
76 gd
->ram_size
= get_ram_size((void *)CONFIG_SYS_SDRAM_BASE
,
77 CONFIG_SYS_SDRAM_SIZE
);
81 #define AT24MAC_MAC_OFFSET 0x9a
83 #ifdef CONFIG_MISC_INIT_R
86 #ifdef CONFIG_I2C_EEPROM
87 at91_set_ethaddr(AT24MAC_MAC_OFFSET
);
95 #ifdef CONFIG_SPL_BUILD
96 void spl_board_init(void)
100 static void ddrc_conf(struct atmel_mpddrc_config
*ddrc
)
102 ddrc
->md
= (ATMEL_MPDDRC_MD_DBW_32_BITS
| ATMEL_MPDDRC_MD_DDR3_SDRAM
);
104 ddrc
->cr
= (ATMEL_MPDDRC_CR_NC_COL_10
|
105 ATMEL_MPDDRC_CR_NR_ROW_14
|
106 ATMEL_MPDDRC_CR_CAS_DDR_CAS5
|
107 ATMEL_MPDDRC_CR_DIC_DS
|
108 ATMEL_MPDDRC_CR_DIS_DLL
|
109 ATMEL_MPDDRC_CR_NB_8BANKS
|
110 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
|
111 ATMEL_MPDDRC_CR_UNAL_SUPPORTED
);
115 ddrc
->tpr0
= (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET
|
116 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET
|
117 4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET
|
118 9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET
|
119 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET
|
120 4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET
|
121 4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET
|
122 4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET
);
124 ddrc
->tpr1
= (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET
|
125 29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET
|
126 0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET
|
127 3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET
);
129 ddrc
->tpr2
= (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET
|
130 0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET
|
131 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET
|
132 4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET
|
133 7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET
);
138 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
139 struct atmel_mpddr
*mpddrc
= (struct atmel_mpddr
*)ATMEL_BASE_MPDDRC
;
140 struct atmel_mpddrc_config ddrc_config
;
143 ddrc_conf(&ddrc_config
);
145 at91_periph_clk_enable(ATMEL_ID_MPDDRC
);
146 writel(AT91_PMC_DDR
, &pmc
->scer
);
148 reg
= readl(&mpddrc
->io_calibr
);
149 reg
&= ~ATMEL_MPDDRC_IO_CALIBR_RDIV
;
150 reg
|= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55
;
151 reg
&= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO
;
152 reg
|= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
153 writel(reg
, &mpddrc
->io_calibr
);
155 writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE
,
156 &mpddrc
->rd_data_path
);
158 ddr3_init(ATMEL_BASE_MPDDRC
, ATMEL_BASE_DDRCS
, &ddrc_config
);
160 writel(0x3, &mpddrc
->cal_mr4
);
161 writel(64, &mpddrc
->tim_cal
);
164 void at91_pmc_init(void)
166 struct at91_pmc
*pmc
= (struct at91_pmc
*)ATMEL_BASE_PMC
;
170 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
171 * so we need to slow down and configure MCKR accordingly.
172 * This is why we have a special flavor of the switching function.
174 tmp
= AT91_PMC_MCKR_PLLADIV_2
|
175 AT91_PMC_MCKR_MDIV_3
|
176 AT91_PMC_MCKR_CSS_MAIN
;
177 at91_mck_init_down(tmp
);
179 tmp
= AT91_PMC_PLLAR_29
|
180 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
181 AT91_PMC_PLLXR_MUL(82) |
182 AT91_PMC_PLLXR_DIV(1);
185 writel(0x0 << 8, &pmc
->pllicpr
);
187 tmp
= AT91_PMC_MCKR_H32MXDIV
|
188 AT91_PMC_MCKR_PLLADIV_2
|
189 AT91_PMC_MCKR_MDIV_3
|
190 AT91_PMC_MCKR_CSS_PLLA
;