board/atmel/sama5d3xek/sama5d3xek.c

   1 /*
   2  * Copyright (C) 2012 - 2013 Atmel Corporation
   3  * Bo Shen <voice.shen@atmel.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/sama5d3_smc.h>
  11 #include <asm/arch/at91_common.h>
  12 #include <asm/arch/at91_rstc.h>
  13 #include <asm/arch/gpio.h>
  14 #include <asm/arch/clk.h>
  15 #include <debug_uart.h>
  16 #include <lcd.h>
  17 #include <linux/ctype.h>
  18 #include <atmel_hlcdc.h>
  19 #include <phy.h>
  20 #include <micrel.h>
  21 #include <spl.h>
  22 #include <asm/arch/atmel_mpddrc.h>
  23 #include <asm/arch/at91_wdt.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /* ------------------------------------------------------------------------- */
  28 /*
  29  * Miscelaneous platform dependent initialisations
  30  */
  31
  32 #ifdef CONFIG_NAND_ATMEL
  33 void sama5d3xek_nand_hw_init(void)
  34 {
  35         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  36
  37         at91_periph_clk_enable(ATMEL_ID_SMC);
  38
  39         /* Configure SMC CS3 for NAND/SmartMedia */
  40         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
  41                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
  42                &smc->cs[3].setup);
  43         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  44                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
  45                &smc->cs[3].pulse);
  46         writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  47                &smc->cs[3].cycle);
  48         writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
  49                AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
  50                AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
  51                AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  52         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  53                AT91_SMC_MODE_EXNW_DISABLE |
  54 #ifdef CONFIG_SYS_NAND_DBW_16
  55                AT91_SMC_MODE_DBW_16 |
  56 #else /* CONFIG_SYS_NAND_DBW_8 */
  57                AT91_SMC_MODE_DBW_8 |
  58 #endif
  59                AT91_SMC_MODE_TDF_CYCLE(3),
  60                &smc->cs[3].mode);
  61 }
  62 #endif
  63
  64 #ifdef CONFIG_MTD_NOR_FLASH
  65 static void sama5d3xek_nor_hw_init(void)
  66 {
  67         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  68
  69         at91_periph_clk_enable(ATMEL_ID_SMC);
  70
  71         /* Configure SMC CS0 for NOR flash */
  72         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  73                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  74                &smc->cs[0].setup);
  75         writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
  76                AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
  77                &smc->cs[0].pulse);
  78         writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
  79                &smc->cs[0].cycle);
  80         writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0)  |
  81                AT91_SMC_TIMINGS_TAR(0)  | AT91_SMC_TIMINGS_TRR(0)   |
  82                AT91_SMC_TIMINGS_TWB(0)  | AT91_SMC_TIMINGS_RBNSEL(0)|
  83                AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
  84         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  85                AT91_SMC_MODE_EXNW_DISABLE |
  86                AT91_SMC_MODE_DBW_16 |
  87                AT91_SMC_MODE_TDF_CYCLE(1),
  88                &smc->cs[0].mode);
  89
  90         /* Address pin (A1 ~ A23) configuration */
  91         at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0);
  92         at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0);
  93         at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0);
  94         at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0);
  95         at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0);
  96         at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0);
  97         at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0);
  98         at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0);
  99         at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0);
 100         at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0);
 101         at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0);
 102         at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0);
 103         at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0);
 104         at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0);
 105         at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0);
 106         at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0);
 107         at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0);
 108         at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0);
 109         at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0);
 110         at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0);
 111         at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0);
 112         at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0);
 113         at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0);
 114         /* CS0 pin configuration */
 115         at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0);
 116 }
 117 #endif
 118
 119 #ifdef CONFIG_CMD_USB
 120 static void sama5d3xek_usb_hw_init(void)
 121 {
 122         at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
 123         at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
 124         at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
 125 }
 126 #endif
 127
 128 #ifdef CONFIG_GENERIC_ATMEL_MCI
 129 static void sama5d3xek_mci_hw_init(void)
 130 {
 131         at91_set_pio_output(AT91_PIO_PORTB, 10, 0);     /* MCI0 Power */
 132 }
 133 #endif
 134
 135 #ifdef CONFIG_LCD
 136 vidinfo_t panel_info = {
 137         .vl_col = 800,
 138         .vl_row = 480,
 139         .vl_clk = 24000000,
 140         .vl_bpix = LCD_BPP,
 141         .vl_tft = 1,
 142         .vl_hsync_len = 128,
 143         .vl_left_margin = 64,
 144         .vl_right_margin = 64,
 145         .vl_vsync_len = 2,
 146         .vl_upper_margin = 22,
 147         .vl_lower_margin = 21,
 148         .mmio = ATMEL_BASE_LCDC,
 149 };
 150
 151 void lcd_enable(void)
 152 {
 153 }
 154
 155 void lcd_disable(void)
 156 {
 157 }
 158
 159 static void sama5d3xek_lcd_hw_init(void)
 160 {
 161         gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
 162
 163         /* The higher 8 bit of LCD is board related */
 164         at91_pio3_set_c_periph(AT91_PIO_PORTC, 14, 0);  /* LCDD16 */
 165         at91_pio3_set_c_periph(AT91_PIO_PORTC, 13, 0);  /* LCDD17 */
 166         at91_pio3_set_c_periph(AT91_PIO_PORTC, 12, 0);  /* LCDD18 */
 167         at91_pio3_set_c_periph(AT91_PIO_PORTC, 11, 0);  /* LCDD19 */
 168         at91_pio3_set_c_periph(AT91_PIO_PORTC, 10, 0);  /* LCDD20 */
 169         at91_pio3_set_c_periph(AT91_PIO_PORTC, 15, 0);  /* LCDD21 */
 170         at91_pio3_set_c_periph(AT91_PIO_PORTE, 27, 0);  /* LCDD22 */
 171         at91_pio3_set_c_periph(AT91_PIO_PORTE, 28, 0);  /* LCDD23 */
 172
 173         /* Configure lower 16 bit of LCD and enable clock */
 174         at91_lcd_hw_init();
 175 }
 176
 177 #ifdef CONFIG_LCD_INFO
 178 #include <nand.h>
 179 #include <version.h>
 180
 181 void lcd_show_board_info(void)
 182 {
 183         ulong dram_size;
 184         uint64_t nand_size;
 185         int i;
 186         char temp[32];
 187
 188         lcd_printf("%s\n", U_BOOT_VERSION);
 189         lcd_printf("(C) 2013 ATMEL Corp\n");
 190         lcd_printf("at91@atmel.com\n");
 191         lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
 192                    strmhz(temp, get_cpu_clk_rate()));
 193
 194         dram_size = 0;
 195         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 196                 dram_size += gd->bd->bi_dram[i].size;
 197
 198         nand_size = 0;
 199 #ifdef CONFIG_NAND_ATMEL
 200         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 201                 nand_size += get_nand_dev_by_index(i)->size;
 202 #endif
 203         lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
 204                    dram_size >> 20, nand_size >> 20);
 205 }
 206 #endif /* CONFIG_LCD_INFO */
 207 #endif /* CONFIG_LCD */
 208
 209 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 210 void board_debug_uart_init(void)
 211 {
 212         at91_seriald_hw_init();
 213 }
 214 #endif
 215
 216 #ifdef CONFIG_BOARD_EARLY_INIT_F
 217 int board_early_init_f(void)
 218 {
 219 #ifdef CONFIG_DEBUG_UART
 220         debug_uart_init();
 221 #endif
 222         return 0;
 223 }
 224 #endif
 225
 226 int board_init(void)
 227 {
 228         /* adress of boot parameters */
 229         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 230
 231 #ifdef CONFIG_NAND_ATMEL
 232         sama5d3xek_nand_hw_init();
 233 #endif
 234 #ifdef CONFIG_MTD_NOR_FLASH
 235         sama5d3xek_nor_hw_init();
 236 #endif
 237 #ifdef CONFIG_CMD_USB
 238         sama5d3xek_usb_hw_init();
 239 #endif
 240 #ifdef CONFIG_GENERIC_ATMEL_MCI
 241         sama5d3xek_mci_hw_init();
 242 #endif
 243 #ifdef CONFIG_LCD
 244         if (has_lcdc())
 245                 sama5d3xek_lcd_hw_init();
 246 #endif
 247         return 0;
 248 }
 249
 250 int dram_init(void)
 251 {
 252         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 253                                     CONFIG_SYS_SDRAM_SIZE);
 254         return 0;
 255 }
 256
 257 #ifdef CONFIG_BOARD_LATE_INIT
 258 int board_late_init(void)
 259 {
 260 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 261         const int MAX_STR_LEN = 32;
 262         char name[MAX_STR_LEN], *p;
 263         int i;
 264
 265         strncpy(name, get_cpu_name(), MAX_STR_LEN);
 266         for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++)
 267                 *p = tolower(*p);
 268
 269         strcat(name, "ek.dtb");
 270         setenv("dtb_name", name);
 271 #endif
 272         return 0;
 273 }
 274 #endif
 275
 276 /* SPL */
 277 #ifdef CONFIG_SPL_BUILD
 278 void spl_board_init(void)
 279 {
 280 #if CONFIG_SYS_USE_NANDFLASH
 281         sama5d3xek_nand_hw_init();
 282 #endif
 283 }
 284
 285 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 286 {
 287         ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 288
 289         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 290                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 291                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 292                     ATMEL_MPDDRC_CR_ENRDM_ON |
 293                     ATMEL_MPDDRC_CR_NB_8BANKS |
 294                     ATMEL_MPDDRC_CR_NDQS_DISABLED |
 295                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 296                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 297         /*
 298          * As the DDR2-SDRAm device requires a refresh time is 7.8125us
 299          * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
 300          */
 301         ddr2->rtr = 0x411;
 302
 303         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 304                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 305                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 306                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 307                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 308                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 309                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 310                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 311
 312         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 313                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 314                       28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 315                       26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 316
 317         ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
 318                       2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 319                       2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 320                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 321                       8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 322 }
 323
 324 void mem_init(void)
 325 {
 326         struct atmel_mpddrc_config ddr2;
 327
 328         ddr2_conf(&ddr2);
 329
 330         /* Enable MPDDR clock */
 331         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 332         at91_system_clk_enable(AT91_PMC_DDR);
 333
 334         /* DDRAM2 Controller initialize */
 335         ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 336 }
 337
 338 void at91_pmc_init(void)
 339 {
 340         u32 tmp;
 341
 342         tmp = AT91_PMC_PLLAR_29 |
 343               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 344               AT91_PMC_PLLXR_MUL(43) |
 345               AT91_PMC_PLLXR_DIV(1);
 346         at91_plla_init(tmp);
 347
 348         at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
 349
 350         tmp = AT91_PMC_MCKR_MDIV_4 |
 351               AT91_PMC_MCKR_CSS_PLLA;
 352         at91_mck_init(tmp);
 353 }
 354 #endif