board/atmel/sama5d4_xplained/sama5d4_xplained.c

   1 /*
   2  * Copyright (C) 2014 Atmel
   3  *                    Bo Shen <voice.shen@atmel.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/at91_common.h>
  11 #include <asm/arch/at91_rstc.h>
  12 #include <asm/arch/atmel_mpddrc.h>
  13 #include <asm/arch/gpio.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/sama5d3_smc.h>
  16 #include <asm/arch/sama5d4.h>
  17 #include <atmel_hlcdc.h>
  18 #include <lcd.h>
  19 #include <nand.h>
  20 #include <version.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #ifdef CONFIG_NAND_ATMEL
  25 static void sama5d4_xplained_nand_hw_init(void)
  26 {
  27         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  28
  29         at91_periph_clk_enable(ATMEL_ID_SMC);
  30
  31         /* Configure SMC CS3 for NAND */
  32         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  33                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  34                &smc->cs[3].setup);
  35         writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
  36                AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
  37                &smc->cs[3].pulse);
  38         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  39                &smc->cs[3].cycle);
  40         writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
  41                AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
  42                AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3)|
  43                AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  44         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  45                AT91_SMC_MODE_EXNW_DISABLE |
  46                AT91_SMC_MODE_DBW_8 |
  47                AT91_SMC_MODE_TDF_CYCLE(3),
  48                &smc->cs[3].mode);
  49
  50         at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);   /* D0 */
  51         at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);   /* D1 */
  52         at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);   /* D2 */
  53         at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);   /* D3 */
  54         at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);   /* D4 */
  55         at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);  /* D5 */
  56         at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);  /* D6 */
  57         at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);  /* D7 */
  58         at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);  /* RE */
  59         at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);  /* WE */
  60         at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1);  /* NCS */
  61         at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1);  /* RDY */
  62         at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1);  /* ALE */
  63         at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1);  /* CLE */
  64 }
  65 #endif
  66
  67 #ifdef CONFIG_CMD_USB
  68 static void sama5d4_xplained_usb_hw_init(void)
  69 {
  70         at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
  71         at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
  72 }
  73 #endif
  74
  75 #ifdef CONFIG_LCD
  76 vidinfo_t panel_info = {
  77         .vl_col = 480,
  78         .vl_row = 272,
  79         .vl_clk = 9000000,
  80         .vl_bpix = LCD_BPP,
  81         .vl_tft = 1,
  82         .vl_hsync_len = 41,
  83         .vl_left_margin = 2,
  84         .vl_right_margin = 2,
  85         .vl_vsync_len = 11,
  86         .vl_upper_margin = 2,
  87         .vl_lower_margin = 2,
  88         .mmio = ATMEL_BASE_LCDC,
  89 };
  90
  91 /* No power up/down pin for the LCD pannel */
  92 void lcd_enable(void)   { /* Empty! */ }
  93 void lcd_disable(void)  { /* Empty! */ }
  94
  95 unsigned int has_lcdc(void)
  96 {
  97         return 1;
  98 }
  99
 100 static void sama5d4_xplained_lcd_hw_init(void)
 101 {
 102         at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0);  /* LCDPWM */
 103         at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0);  /* LCDDISP */
 104         at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0);  /* LCDVSYNC */
 105         at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0);  /* LCDHSYNC */
 106         at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0);  /* LCDDOTCK */
 107         at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0);  /* LCDDEN */
 108
 109         at91_pio3_set_a_periph(AT91_PIO_PORTA,  0, 0);  /* LCDD0 */
 110         at91_pio3_set_a_periph(AT91_PIO_PORTA,  1, 0);  /* LCDD1 */
 111         at91_pio3_set_a_periph(AT91_PIO_PORTA,  2, 0);  /* LCDD2 */
 112         at91_pio3_set_a_periph(AT91_PIO_PORTA,  3, 0);  /* LCDD3 */
 113         at91_pio3_set_a_periph(AT91_PIO_PORTA,  4, 0);  /* LCDD4 */
 114         at91_pio3_set_a_periph(AT91_PIO_PORTA,  5, 0);  /* LCDD5 */
 115         at91_pio3_set_a_periph(AT91_PIO_PORTA,  6, 0);  /* LCDD6 */
 116         at91_pio3_set_a_periph(AT91_PIO_PORTA,  7, 0);  /* LCDD7 */
 117
 118         at91_pio3_set_a_periph(AT91_PIO_PORTA,  8, 0);  /* LCDD9 */
 119         at91_pio3_set_a_periph(AT91_PIO_PORTA,  9, 0);  /* LCDD8 */
 120         at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0);  /* LCDD10 */
 121         at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0);  /* LCDD11 */
 122         at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0);  /* LCDD12 */
 123         at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0);  /* LCDD13 */
 124         at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0);  /* LCDD14 */
 125         at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0);  /* LCDD15 */
 126
 127         at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0);  /* LCDD16 */
 128         at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0);  /* LCDD17 */
 129         at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0);  /* LCDD18 */
 130         at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0);  /* LCDD19 */
 131         at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0);  /* LCDD20 */
 132         at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0);  /* LCDD21 */
 133         at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0);  /* LCDD22 */
 134         at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0);  /* LCDD23 */
 135
 136         /* Enable clock */
 137         at91_periph_clk_enable(ATMEL_ID_LCDC);
 138 }
 139
 140 #ifdef CONFIG_LCD_INFO
 141 void lcd_show_board_info(void)
 142 {
 143         ulong dram_size, nand_size;
 144         int i;
 145         char temp[32];
 146
 147         lcd_printf("%s\n", U_BOOT_VERSION);
 148         lcd_printf("2014 ATMEL Corp\n");
 149         lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
 150                    strmhz(temp, get_cpu_clk_rate()));
 151
 152         dram_size = 0;
 153         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 154                 dram_size += gd->bd->bi_dram[i].size;
 155
 156         nand_size = 0;
 157 #ifdef CONFIG_NAND_ATMEL
 158         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 159                 nand_size += nand_info[i]->size;
 160 #endif
 161         lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
 162                    dram_size >> 20, nand_size >> 20);
 163 }
 164 #endif /* CONFIG_LCD_INFO */
 165
 166 #endif /* CONFIG_LCD */
 167
 168 static void sama5d4_xplained_serial3_hw_init(void)
 169 {
 170         at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);  /* TXD3 */
 171         at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);  /* RXD3 */
 172
 173         /* Enable clock */
 174         at91_periph_clk_enable(ATMEL_ID_USART3);
 175 }
 176
 177 int board_early_init_f(void)
 178 {
 179         sama5d4_xplained_serial3_hw_init();
 180
 181         return 0;
 182 }
 183
 184 int board_init(void)
 185 {
 186         /* adress of boot parameters */
 187         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 188
 189 #ifdef CONFIG_NAND_ATMEL
 190         sama5d4_xplained_nand_hw_init();
 191 #endif
 192 #ifdef CONFIG_LCD
 193         sama5d4_xplained_lcd_hw_init();
 194 #endif
 195 #ifdef CONFIG_CMD_USB
 196         sama5d4_xplained_usb_hw_init();
 197 #endif
 198
 199         return 0;
 200 }
 201
 202 int dram_init(void)
 203 {
 204         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 205                                     CONFIG_SYS_SDRAM_SIZE);
 206         return 0;
 207 }
 208
 209 /* SPL */
 210 #ifdef CONFIG_SPL_BUILD
 211 void spl_board_init(void)
 212 {
 213 #if CONFIG_SYS_USE_NANDFLASH
 214         sama5d4_xplained_nand_hw_init();
 215 #endif
 216 }
 217
 218 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 219 {
 220         ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 221
 222         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 223                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 224                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 225                     ATMEL_MPDDRC_CR_NB_8BANKS |
 226                     ATMEL_MPDDRC_CR_NDQS_DISABLED |
 227                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 228                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 229
 230         ddr2->rtr = 0x2b0;
 231
 232         ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 233                       3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 234                       3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 235                       10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 236                       3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 237                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 238                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 239                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 240
 241         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 242                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 243                       25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 244                       23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 245
 246         ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
 247                       2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 248                       3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 249                       2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 250                       8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 251 }
 252
 253 void mem_init(void)
 254 {
 255         struct atmel_mpddrc_config ddr2;
 256
 257         ddr2_conf(&ddr2);
 258
 259         /* Enable MPDDR clock */
 260         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 261         at91_system_clk_enable(AT91_PMC_DDR);
 262
 263         /* DDRAM2 Controller initialize */
 264         ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 265 }
 266
 267 void at91_pmc_init(void)
 268 {
 269         u32 tmp;
 270
 271         tmp = AT91_PMC_PLLAR_29 |
 272               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 273               AT91_PMC_PLLXR_MUL(87) |
 274               AT91_PMC_PLLXR_DIV(1);
 275         at91_plla_init(tmp);
 276
 277         at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
 278
 279         tmp = AT91_PMC_MCKR_H32MXDIV |
 280               AT91_PMC_MCKR_PLLADIV_2 |
 281               AT91_PMC_MCKR_MDIV_3 |
 282               AT91_PMC_MCKR_CSS_PLLA;
 283         at91_mck_init(tmp);
 284 }
 285 #endif