board/atmel/sama5d4ek/sama5d4ek.c

   1 /*
   2  * Copyright (C) 2014 Atmel
   3  *                    Bo Shen <voice.shen@atmel.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/at91_common.h>
  11 #include <asm/arch/at91_rstc.h>
  12 #include <asm/arch/atmel_mpddrc.h>
  13 #include <asm/arch/gpio.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/sama5d3_smc.h>
  16 #include <asm/arch/sama5d4.h>
  17 #include <atmel_hlcdc.h>
  18 #include <debug_uart.h>
  19 #include <lcd.h>
  20 #include <nand.h>
  21 #include <version.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #ifdef CONFIG_NAND_ATMEL
  26 static void sama5d4ek_nand_hw_init(void)
  27 {
  28         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  29
  30         at91_periph_clk_enable(ATMEL_ID_SMC);
  31
  32         /* Configure SMC CS3 for NAND */
  33         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  34                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  35                &smc->cs[3].setup);
  36         writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
  37                AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
  38                &smc->cs[3].pulse);
  39         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  40                &smc->cs[3].cycle);
  41         writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
  42                AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
  43                AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3)|
  44                AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  45         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  46                AT91_SMC_MODE_EXNW_DISABLE |
  47                AT91_SMC_MODE_DBW_8 |
  48                AT91_SMC_MODE_TDF_CYCLE(3),
  49                &smc->cs[3].mode);
  50
  51         at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);   /* D0 */
  52         at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);   /* D1 */
  53         at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);   /* D2 */
  54         at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);   /* D3 */
  55         at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);   /* D4 */
  56         at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);  /* D5 */
  57         at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);  /* D6 */
  58         at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);  /* D7 */
  59         at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);  /* RE */
  60         at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);  /* WE */
  61         at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1);  /* NCS */
  62         at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1);  /* RDY */
  63         at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1);  /* ALE */
  64         at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1);  /* CLE */
  65 }
  66 #endif
  67
  68 #ifdef CONFIG_CMD_USB
  69 static void sama5d4ek_usb_hw_init(void)
  70 {
  71         at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
  72         at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
  73         at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
  74 }
  75 #endif
  76
  77 #ifdef CONFIG_LCD
  78 vidinfo_t panel_info = {
  79         .vl_col = 800,
  80         .vl_row = 480,
  81         .vl_clk = 33260000,
  82         .vl_bpix = LCD_BPP,
  83         .vl_tft = 1,
  84         .vl_hsync_len = 5,
  85         .vl_left_margin = 128,
  86         .vl_right_margin = 0,
  87         .vl_vsync_len = 5,
  88         .vl_upper_margin = 23,
  89         .vl_lower_margin = 22,
  90         .mmio = ATMEL_BASE_LCDC,
  91 };
  92
  93 /* No power up/down pin for the LCD pannel */
  94 void lcd_enable(void)   { /* Empty! */ }
  95 void lcd_disable(void)  { /* Empty! */ }
  96
  97 unsigned int has_lcdc(void)
  98 {
  99         return 1;
 100 }
 101
 102 static void sama5d4ek_lcd_hw_init(void)
 103 {
 104         at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0);  /* LCDPWM */
 105         at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0);  /* LCDDISP */
 106         at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0);  /* LCDVSYNC */
 107         at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0);  /* LCDHSYNC */
 108         at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0);  /* LCDDOTCK */
 109         at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0);  /* LCDDEN */
 110
 111         at91_pio3_set_a_periph(AT91_PIO_PORTA,  2, 0);  /* LCDD2 */
 112         at91_pio3_set_a_periph(AT91_PIO_PORTA,  3, 0);  /* LCDD3 */
 113         at91_pio3_set_a_periph(AT91_PIO_PORTA,  4, 0);  /* LCDD4 */
 114         at91_pio3_set_a_periph(AT91_PIO_PORTA,  5, 0);  /* LCDD5 */
 115         at91_pio3_set_a_periph(AT91_PIO_PORTA,  6, 0);  /* LCDD6 */
 116         at91_pio3_set_a_periph(AT91_PIO_PORTA,  7, 0);  /* LCDD7 */
 117
 118         at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0);  /* LCDD10 */
 119         at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0);  /* LCDD11 */
 120         at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0);  /* LCDD12 */
 121         at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0);  /* LCDD13 */
 122         at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0);  /* LCDD14 */
 123         at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0);  /* LCDD15 */
 124
 125         at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0);  /* LCDD18 */
 126         at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0);  /* LCDD19 */
 127         at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0);  /* LCDD20 */
 128         at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0);  /* LCDD21 */
 129         at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0);  /* LCDD22 */
 130         at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0);  /* LCDD23 */
 131
 132         /* Enable clock */
 133         at91_periph_clk_enable(ATMEL_ID_LCDC);
 134 }
 135
 136 #ifdef CONFIG_LCD_INFO
 137 void lcd_show_board_info(void)
 138 {
 139         ulong dram_size, nand_size;
 140         int i;
 141         char temp[32];
 142
 143         lcd_printf("%s\n", U_BOOT_VERSION);
 144         lcd_printf("2014 ATMEL Corp\n");
 145         lcd_printf("at91@atmel.com\n");
 146         lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
 147                    strmhz(temp, get_cpu_clk_rate()));
 148
 149         dram_size = 0;
 150         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 151                 dram_size += gd->bd->bi_dram[i].size;
 152
 153         nand_size = 0;
 154 #ifdef CONFIG_NAND_ATMEL
 155         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 156                 nand_size += get_nand_dev_by_index(i)->size;
 157 #endif
 158         lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
 159                    dram_size >> 20, nand_size >> 20);
 160 }
 161 #endif /* CONFIG_LCD_INFO */
 162
 163 #endif /* CONFIG_LCD */
 164
 165 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 166 static void sama5d4ek_serial3_hw_init(void)
 167 {
 168         at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);  /* TXD3 */
 169         at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);  /* RXD3 */
 170
 171         /* Enable clock */
 172         at91_periph_clk_enable(ATMEL_ID_USART3);
 173 }
 174
 175 void board_debug_uart_init(void)
 176 {
 177         sama5d4ek_serial3_hw_init();
 178 }
 179 #endif
 180
 181 #ifdef CONFIG_BOARD_EARLY_INIT_F
 182 int board_early_init_f(void)
 183 {
 184 #ifdef CONFIG_DEBUG_UART
 185         debug_uart_init();
 186 #endif
 187         return 0;
 188 }
 189 #endif
 190
 191 int board_init(void)
 192 {
 193         /* adress of boot parameters */
 194         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 195
 196 #ifdef CONFIG_NAND_ATMEL
 197         sama5d4ek_nand_hw_init();
 198 #endif
 199 #ifdef CONFIG_LCD
 200         sama5d4ek_lcd_hw_init();
 201 #endif
 202 #ifdef CONFIG_CMD_USB
 203         sama5d4ek_usb_hw_init();
 204 #endif
 205
 206         return 0;
 207 }
 208
 209 int dram_init(void)
 210 {
 211         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 212                                     CONFIG_SYS_SDRAM_SIZE);
 213         return 0;
 214 }
 215
 216 /* SPL */
 217 #ifdef CONFIG_SPL_BUILD
 218 void spl_board_init(void)
 219 {
 220 #if CONFIG_NAND_BOOT
 221         sama5d4ek_nand_hw_init();
 222 #endif
 223 }
 224
 225 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 226 {
 227         ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 228
 229         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 230                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 231                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 232                     ATMEL_MPDDRC_CR_NB_8BANKS |
 233                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 234                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 235
 236         ddr2->rtr = 0x2b0;
 237
 238         ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 239                       3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 240                       3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 241                       10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 242                       3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 243                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 244                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 245                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 246
 247         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 248                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 249                       25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 250                       23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 251
 252         ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
 253                       2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 254                       3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 255                       2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 256                       8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 257 }
 258
 259 void mem_init(void)
 260 {
 261         struct atmel_mpddrc_config ddr2;
 262         const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
 263         u32 tmp;
 264
 265         ddr2_conf(&ddr2);
 266
 267         /* Enable MPDDR clock */
 268         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 269         at91_system_clk_enable(AT91_PMC_DDR);
 270
 271         tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE;
 272         writel(tmp, &mpddr->rd_data_path);
 273
 274         tmp = readl(&mpddr->io_calibr);
 275         tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV |
 276                ATMEL_MPDDRC_IO_CALIBR_TZQIO |
 277                ATMEL_MPDDRC_IO_CALIBR_CALCODEP |
 278                ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) |
 279                ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 |
 280                ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) |
 281                ATMEL_MPDDRC_IO_CALIBR_EN_CALIB;
 282         writel(tmp, &mpddr->io_calibr);
 283
 284         /* DDRAM2 Controller initialize */
 285         ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 286 }
 287
 288 void at91_pmc_init(void)
 289 {
 290         u32 tmp;
 291
 292         tmp = AT91_PMC_PLLAR_29 |
 293               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 294               AT91_PMC_PLLXR_MUL(87) |
 295               AT91_PMC_PLLXR_DIV(1);
 296         at91_plla_init(tmp);
 297
 298         at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
 299
 300         tmp = AT91_PMC_MCKR_H32MXDIV |
 301               AT91_PMC_MCKR_PLLADIV_2 |
 302               AT91_PMC_MCKR_MDIV_3 |
 303               AT91_PMC_MCKR_CSS_PLLA;
 304         at91_mck_init(tmp);
 305 }
 306 #endif