board/bf533-stamp/u-boot.lds.S

   1 /*
   2  * U-boot - u-boot.lds.S
   3  *
   4  * Copyright (c) 2005-2008 Analog Device Inc.
   5  *
   6  * (C) Copyright 2000-2004
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <asm/blackfin.h>
  30 #undef ALIGN
  31
  32 /* If we don't actually load anything into L1 data, this will avoid
  33  * a syntax error.  If we do actually load something into L1 data,
  34  * we'll get a linker memory load error (which is what we'd want).
  35  * This is here in the first place so we can quickly test building
  36  * for different CPU's which may lack non-cache L1 data.
  37  */
  38 #ifndef L1_DATA_B_SRAM
  39 # define L1_DATA_B_SRAM      CONFIG_SYS_MONITOR_BASE
  40 # define L1_DATA_B_SRAM_SIZE 0
  41 #endif
  42
  43 OUTPUT_ARCH(bfin)
  44
  45 /* The 0xC offset is so we don't clobber the tiny LDR jump block. */
  46 MEMORY
  47 {
  48         ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
  49         l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
  50         l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
  51 }
  52
  53 SECTIONS
  54 {
  55         .text :
  56         {
  57 #ifdef ENV_IS_EMBEDDED
  58                 /* WARNING - the following is hand-optimized to fit within
  59                  * the sector before the environment sector. If it throws
  60                  * an error during compilation remove an object here to get
  61                  * it linked after the configuration sector.
  62                  */
  63
  64                 cpu/blackfin/start.o            (.text)
  65                 cpu/blackfin/traps.o            (.text)
  66                 cpu/blackfin/interrupt.o        (.text)
  67                 cpu/blackfin/serial.o           (.text)
  68                 common/dlmalloc.o               (.text)
  69                 lib_generic/crc32.o             (.text)
  70
  71                 . = DEFINED(env_offset) ? env_offset : .;
  72                 common/env_embedded.o   (.text)
  73 #endif
  74
  75                 *(.text .text.*)
  76         } >ram
  77
  78         .rodata :
  79         {
  80                 . = ALIGN(4);
  81                 *(.rodata .rodata.*)
  82                 *(.rodata1)
  83                 *(.eh_frame)
  84                 . = ALIGN(4);
  85         } >ram
  86
  87         .data :
  88         {
  89                 . = ALIGN(256);
  90                 *(.data .data.*)
  91                 *(.data1)
  92                 *(.sdata)
  93                 *(.sdata2)
  94                 *(.dynamic)
  95                 CONSTRUCTORS
  96         } >ram
  97
  98         .u_boot_cmd :
  99         {
 100                 ___u_boot_cmd_start = .;
 101                 *(.u_boot_cmd)
 102                 ___u_boot_cmd_end = .;
 103         } >ram
 104
 105         .text_l1 :
 106         {
 107                 . = ALIGN(4);
 108                 __stext_l1 = .;
 109                 *(.l1.text)
 110                 . = ALIGN(4);
 111                 __etext_l1 = .;
 112         } >l1_code AT>ram
 113         __stext_l1_lma = LOADADDR(.text_l1);
 114
 115         .data_l1 :
 116         {
 117                 . = ALIGN(4);
 118                 __sdata_l1 = .;
 119                 *(.l1.data)
 120                 *(.l1.bss)
 121                 . = ALIGN(4);
 122                 __edata_l1 = .;
 123         } >l1_data AT>ram
 124         __sdata_l1_lma = LOADADDR(.data_l1);
 125
 126         .bss :
 127         {
 128                 . = ALIGN(4);
 129                 __bss_start = .;
 130                 *(.sbss) *(.scommon)
 131                 *(.dynbss)
 132                 *(.bss .bss.*)
 133                 *(COMMON)
 134                 __bss_end = .;
 135         } >ram
 136 }