board/bf537-stamp/nand.c

   1 /*
   2  * Copyright (c) 2006-2007 Analog Devices Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25
  26 #include <nand.h>
  27
  28 #define CONCAT(a,b,c,d) a ## b ## c ## d
  29 #define PORT(a,b)  CONCAT(pPORT,a,b,)
  30
  31 #ifndef CONFIG_NAND_GPIO_PORT
  32 #define CONFIG_NAND_GPIO_PORT F
  33 #endif
  34
  35 /*
  36  * hardware specific access to control-lines
  37  */
  38 static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  39 {
  40         register struct nand_chip *this = mtd->priv;
  41         u32 IO_ADDR_W = (u32) this->IO_ADDR_W;
  42
  43         if (ctrl & NAND_CTRL_CHANGE) {
  44                 if (ctrl & NAND_CLE)
  45                         IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_CLE;
  46                 else
  47                         IO_ADDR_W = CONFIG_SYS_NAND_BASE;
  48                 if (ctrl & NAND_ALE)
  49                         IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_ALE;
  50                 else
  51                         IO_ADDR_W = CONFIG_SYS_NAND_BASE;
  52                 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
  53         }
  54         this->IO_ADDR_R = this->IO_ADDR_W;
  55
  56         /* Drain the writebuffer */
  57         SSYNC();
  58
  59         if (cmd != NAND_CMD_NONE)
  60                 writeb(cmd, this->IO_ADDR_W);
  61 }
  62
  63 int bfin_device_ready(struct mtd_info *mtd)
  64 {
  65         int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
  66         SSYNC();
  67         return ret;
  68 }
  69
  70 /*
  71  * Board-specific NAND initialization. The following members of the
  72  * argument are board-specific (per include/linux/mtd/nand.h):
  73  * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
  74  * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
  75  * - cmd_ctrl: hardwarespecific function for accesing control-lines
  76  * - dev_ready: hardwarespecific function for  accesing device ready/busy line
  77  * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
  78  *   only be provided if a hardware ECC is available
  79  * - ecc.mode: mode of ecc, see defines
  80  * - chip_delay: chip dependent delay for transfering data from array to
  81  *   read regs (tR)
  82  * - options: various chip options. They can partly be set to inform
  83  *   nand_scan about special functionality. See the defines for further
  84  *   explanation
  85  * Members with a "?" were not set in the merged testing-NAND branch,
  86  * so they are not set here either.
  87  */
  88 int board_nand_init(struct nand_chip *nand)
  89 {
  90         *PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
  91         *PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
  92         *PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
  93
  94         nand->cmd_ctrl = bfin_hwcontrol;
  95         nand->ecc.mode = NAND_ECC_SOFT;
  96         nand->dev_ready = bfin_device_ready;
  97         nand->chip_delay = 30;
  98
  99         return 0;
 100 }