]> git.ipfire.org Git - people/ms/u-boot.git/blob - board/boundary/nitrogen6x/nitrogen6x.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxx
[people/ms/u-boot.git] / board / boundary / nitrogen6x / nitrogen6x.c
1 /*
2 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3 * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/sys_proto.h>
14 #include <malloc.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/errno.h>
17 #include <asm/gpio.h>
18 #include <asm/imx-common/iomux-v3.h>
19 #include <asm/imx-common/mxc_i2c.h>
20 #include <asm/imx-common/sata.h>
21 #include <asm/imx-common/spi.h>
22 #include <asm/imx-common/boot_mode.h>
23 #include <asm/imx-common/video.h>
24 #include <mmc.h>
25 #include <fsl_esdhc.h>
26 #include <micrel.h>
27 #include <miiphy.h>
28 #include <netdev.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/mxc_hdmi.h>
31 #include <i2c.h>
32 #include <input.h>
33 #include <netdev.h>
34 #include <usb/ehci-fsl.h>
35
36 DECLARE_GLOBAL_DATA_PTR;
37 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
38
39 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
44 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
45 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46
47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
49
50 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
51 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
52
53 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
54 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
55
56 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
57 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
58 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
59
60 #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
61 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
62 PAD_CTL_SRE_SLOW)
63
64 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
65 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
66 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
67
68 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
69
70 int dram_init(void)
71 {
72 gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
73
74 return 0;
75 }
76
77 static iomux_v3_cfg_t const uart1_pads[] = {
78 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
79 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
80 };
81
82 static iomux_v3_cfg_t const uart2_pads[] = {
83 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
84 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
85 };
86
87 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
88
89 /* I2C1, SGTL5000 */
90 static struct i2c_pads_info i2c_pad_info0 = {
91 .scl = {
92 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
93 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
94 .gp = IMX_GPIO_NR(3, 21)
95 },
96 .sda = {
97 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
98 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
99 .gp = IMX_GPIO_NR(3, 28)
100 }
101 };
102
103 /* I2C2 Camera, MIPI */
104 static struct i2c_pads_info i2c_pad_info1 = {
105 .scl = {
106 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
107 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
108 .gp = IMX_GPIO_NR(4, 12)
109 },
110 .sda = {
111 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
112 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
113 .gp = IMX_GPIO_NR(4, 13)
114 }
115 };
116
117 /* I2C3, J15 - RGB connector */
118 static struct i2c_pads_info i2c_pad_info2 = {
119 .scl = {
120 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
121 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
122 .gp = IMX_GPIO_NR(1, 5)
123 },
124 .sda = {
125 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
126 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
127 .gp = IMX_GPIO_NR(7, 11)
128 }
129 };
130
131 static iomux_v3_cfg_t const usdhc2_pads[] = {
132 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 };
139
140 static iomux_v3_cfg_t const usdhc3_pads[] = {
141 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
148 };
149
150 static iomux_v3_cfg_t const usdhc4_pads[] = {
151 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
157 MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
158 };
159
160 static iomux_v3_cfg_t const enet_pads1[] = {
161 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
162 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
163 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
164 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
165 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
166 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
167 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
168 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
169 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
170 /* pin 35 - 1 (PHY_AD2) on reset */
171 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
172 /* pin 32 - 1 - (MODE0) all */
173 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
174 /* pin 31 - 1 - (MODE1) all */
175 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
176 /* pin 28 - 1 - (MODE2) all */
177 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
178 /* pin 27 - 1 - (MODE3) all */
179 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
180 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
181 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
182 /* pin 42 PHY nRST */
183 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
184 MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
185 };
186
187 static iomux_v3_cfg_t const enet_pads2[] = {
188 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
189 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
190 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
191 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
192 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
193 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
194 };
195
196 static iomux_v3_cfg_t const misc_pads[] = {
197 MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
198 MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
199 MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
200 /* OTG Power enable */
201 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
202 };
203
204 /* wl1271 pads on nitrogen6x */
205 static iomux_v3_cfg_t const wl12xx_pads[] = {
206 (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
207 | MUX_PAD_CTRL(WEAK_PULLDOWN),
208 (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
209 | MUX_PAD_CTRL(OUTPUT_40OHM),
210 (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
211 | MUX_PAD_CTRL(OUTPUT_40OHM),
212 };
213 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
214 #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
215 #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
216
217 /* Button assignments for J14 */
218 static iomux_v3_cfg_t const button_pads[] = {
219 /* Menu */
220 MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
221 /* Back */
222 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
223 /* Labelled Search (mapped to Power under Android) */
224 MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
225 /* Home */
226 MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
227 /* Volume Down */
228 MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
229 /* Volume Up */
230 MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
231 };
232
233 static void setup_iomux_enet(void)
234 {
235 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
236 gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
237 gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
238 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
239 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
240 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
241 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
242 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
243 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
244
245 /* Need delay 10ms according to KSZ9021 spec */
246 udelay(1000 * 10);
247 gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
248 gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
249
250 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
251 udelay(100); /* Wait 100 us before using mii interface */
252 }
253
254 static iomux_v3_cfg_t const usb_pads[] = {
255 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
256 };
257
258 static void setup_iomux_uart(void)
259 {
260 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
261 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
262 }
263
264 #ifdef CONFIG_USB_EHCI_MX6
265 int board_ehci_hcd_init(int port)
266 {
267 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
268
269 /* Reset USB hub */
270 gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
271 mdelay(2);
272 gpio_set_value(IMX_GPIO_NR(7, 12), 1);
273
274 return 0;
275 }
276
277 int board_ehci_power(int port, int on)
278 {
279 if (port)
280 return 0;
281 gpio_set_value(GP_USB_OTG_PWR, on);
282 return 0;
283 }
284
285 #endif
286
287 #ifdef CONFIG_FSL_ESDHC
288 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
289 {USDHC3_BASE_ADDR},
290 {USDHC4_BASE_ADDR},
291 };
292
293 int board_mmc_getcd(struct mmc *mmc)
294 {
295 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
296 int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
297 IMX_GPIO_NR(2, 6);
298
299 gpio_direction_input(gp_cd);
300 return !gpio_get_value(gp_cd);
301 }
302
303 int board_mmc_init(bd_t *bis)
304 {
305 s32 status = 0;
306 u32 index = 0;
307
308 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
309 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
310
311 usdhc_cfg[0].max_bus_width = 4;
312 usdhc_cfg[1].max_bus_width = 4;
313
314 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
315 switch (index) {
316 case 0:
317 imx_iomux_v3_setup_multiple_pads(
318 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
319 break;
320 case 1:
321 imx_iomux_v3_setup_multiple_pads(
322 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
323 break;
324 default:
325 printf("Warning: you configured more USDHC controllers"
326 "(%d) then supported by the board (%d)\n",
327 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
328 return status;
329 }
330
331 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
332 }
333
334 return status;
335 }
336 #endif
337
338 #ifdef CONFIG_MXC_SPI
339 int board_spi_cs_gpio(unsigned bus, unsigned cs)
340 {
341 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
342 }
343
344 static iomux_v3_cfg_t const ecspi1_pads[] = {
345 /* SS1 */
346 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
347 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
348 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
349 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
350 };
351
352 static void setup_spi(void)
353 {
354 imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
355 ARRAY_SIZE(ecspi1_pads));
356 }
357 #endif
358
359 int board_phy_config(struct phy_device *phydev)
360 {
361 /* min rx data delay */
362 ksz9021_phy_extended_write(phydev,
363 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
364 /* min tx data delay */
365 ksz9021_phy_extended_write(phydev,
366 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
367 /* max rx/tx clock delay, min rx/tx control */
368 ksz9021_phy_extended_write(phydev,
369 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
370 if (phydev->drv->config)
371 phydev->drv->config(phydev);
372
373 return 0;
374 }
375
376 int board_eth_init(bd_t *bis)
377 {
378 uint32_t base = IMX_FEC_BASE;
379 struct mii_dev *bus = NULL;
380 struct phy_device *phydev = NULL;
381 int ret;
382
383 setup_iomux_enet();
384
385 #ifdef CONFIG_FEC_MXC
386 bus = fec_get_miibus(base, -1);
387 if (!bus)
388 return 0;
389 /* scan phy 4,5,6,7 */
390 phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
391 if (!phydev) {
392 free(bus);
393 return 0;
394 }
395 printf("using phy at %d\n", phydev->addr);
396 ret = fec_probe(bis, -1, base, bus, phydev);
397 if (ret) {
398 printf("FEC MXC: %s:failed\n", __func__);
399 free(phydev);
400 free(bus);
401 }
402 #endif
403
404 #ifdef CONFIG_CI_UDC
405 /* For otg ethernet*/
406 usb_eth_initialize(bis);
407 #endif
408 return 0;
409 }
410
411 static void setup_buttons(void)
412 {
413 imx_iomux_v3_setup_multiple_pads(button_pads,
414 ARRAY_SIZE(button_pads));
415 }
416
417 #if defined(CONFIG_VIDEO_IPUV3)
418
419 static iomux_v3_cfg_t const backlight_pads[] = {
420 /* Backlight on RGB connector: J15 */
421 MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
422 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
423
424 /* Backlight on LVDS connector: J6 */
425 MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
426 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
427 };
428
429 static iomux_v3_cfg_t const rgb_pads[] = {
430 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
431 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
432 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
433 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
434 MX6_PAD_DI0_PIN4__GPIO4_IO20,
435 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
436 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
437 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
438 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
439 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
440 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
441 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
442 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
443 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
444 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
445 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
446 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
447 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
448 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
449 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
450 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
451 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
452 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
453 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
454 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
455 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
456 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
457 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
458 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
459 };
460
461 static void do_enable_hdmi(struct display_info_t const *dev)
462 {
463 imx_enable_hdmi_phy();
464 }
465
466 static int detect_i2c(struct display_info_t const *dev)
467 {
468 return ((0 == i2c_set_bus_num(dev->bus))
469 &&
470 (0 == i2c_probe(dev->addr)));
471 }
472
473 static void enable_lvds(struct display_info_t const *dev)
474 {
475 struct iomuxc *iomux = (struct iomuxc *)
476 IOMUXC_BASE_ADDR;
477 u32 reg = readl(&iomux->gpr[2]);
478 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
479 writel(reg, &iomux->gpr[2]);
480 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
481 }
482
483 static void enable_lvds_jeida(struct display_info_t const *dev)
484 {
485 struct iomuxc *iomux = (struct iomuxc *)
486 IOMUXC_BASE_ADDR;
487 u32 reg = readl(&iomux->gpr[2]);
488 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
489 |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
490 writel(reg, &iomux->gpr[2]);
491 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
492 }
493
494 static void enable_rgb(struct display_info_t const *dev)
495 {
496 imx_iomux_v3_setup_multiple_pads(
497 rgb_pads,
498 ARRAY_SIZE(rgb_pads));
499 gpio_direction_output(RGB_BACKLIGHT_GP, 1);
500 }
501
502 struct display_info_t const displays[] = {{
503 .bus = 1,
504 .addr = 0x50,
505 .pixfmt = IPU_PIX_FMT_RGB24,
506 .detect = detect_i2c,
507 .enable = do_enable_hdmi,
508 .mode = {
509 .name = "HDMI",
510 .refresh = 60,
511 .xres = 1024,
512 .yres = 768,
513 .pixclock = 15385,
514 .left_margin = 220,
515 .right_margin = 40,
516 .upper_margin = 21,
517 .lower_margin = 7,
518 .hsync_len = 60,
519 .vsync_len = 10,
520 .sync = FB_SYNC_EXT,
521 .vmode = FB_VMODE_NONINTERLACED
522 } }, {
523 .bus = 0,
524 .addr = 0,
525 .pixfmt = IPU_PIX_FMT_RGB24,
526 .detect = NULL,
527 .enable = enable_lvds_jeida,
528 .mode = {
529 .name = "LDB-WXGA",
530 .refresh = 60,
531 .xres = 1280,
532 .yres = 800,
533 .pixclock = 14065,
534 .left_margin = 40,
535 .right_margin = 40,
536 .upper_margin = 3,
537 .lower_margin = 80,
538 .hsync_len = 10,
539 .vsync_len = 10,
540 .sync = FB_SYNC_EXT,
541 .vmode = FB_VMODE_NONINTERLACED
542 } }, {
543 .bus = 0,
544 .addr = 0,
545 .pixfmt = IPU_PIX_FMT_RGB24,
546 .detect = NULL,
547 .enable = enable_lvds,
548 .mode = {
549 .name = "LDB-WXGA-S",
550 .refresh = 60,
551 .xres = 1280,
552 .yres = 800,
553 .pixclock = 14065,
554 .left_margin = 40,
555 .right_margin = 40,
556 .upper_margin = 3,
557 .lower_margin = 80,
558 .hsync_len = 10,
559 .vsync_len = 10,
560 .sync = FB_SYNC_EXT,
561 .vmode = FB_VMODE_NONINTERLACED
562 } }, {
563 .bus = 2,
564 .addr = 0x4,
565 .pixfmt = IPU_PIX_FMT_LVDS666,
566 .detect = detect_i2c,
567 .enable = enable_lvds,
568 .mode = {
569 .name = "Hannstar-XGA",
570 .refresh = 60,
571 .xres = 1024,
572 .yres = 768,
573 .pixclock = 15385,
574 .left_margin = 220,
575 .right_margin = 40,
576 .upper_margin = 21,
577 .lower_margin = 7,
578 .hsync_len = 60,
579 .vsync_len = 10,
580 .sync = FB_SYNC_EXT,
581 .vmode = FB_VMODE_NONINTERLACED
582 } }, {
583 .bus = 0,
584 .addr = 0,
585 .pixfmt = IPU_PIX_FMT_LVDS666,
586 .detect = NULL,
587 .enable = enable_lvds,
588 .mode = {
589 .name = "LG-9.7",
590 .refresh = 60,
591 .xres = 1024,
592 .yres = 768,
593 .pixclock = 15385, /* ~65MHz */
594 .left_margin = 480,
595 .right_margin = 260,
596 .upper_margin = 16,
597 .lower_margin = 6,
598 .hsync_len = 250,
599 .vsync_len = 10,
600 .sync = FB_SYNC_EXT,
601 .vmode = FB_VMODE_NONINTERLACED
602 } }, {
603 .bus = 2,
604 .addr = 0x38,
605 .pixfmt = IPU_PIX_FMT_LVDS666,
606 .detect = detect_i2c,
607 .enable = enable_lvds,
608 .mode = {
609 .name = "wsvga-lvds",
610 .refresh = 60,
611 .xres = 1024,
612 .yres = 600,
613 .pixclock = 15385,
614 .left_margin = 220,
615 .right_margin = 40,
616 .upper_margin = 21,
617 .lower_margin = 7,
618 .hsync_len = 60,
619 .vsync_len = 10,
620 .sync = FB_SYNC_EXT,
621 .vmode = FB_VMODE_NONINTERLACED
622 } }, {
623 .bus = 2,
624 .addr = 0x10,
625 .pixfmt = IPU_PIX_FMT_RGB666,
626 .detect = detect_i2c,
627 .enable = enable_rgb,
628 .mode = {
629 .name = "fusion7",
630 .refresh = 60,
631 .xres = 800,
632 .yres = 480,
633 .pixclock = 33898,
634 .left_margin = 96,
635 .right_margin = 24,
636 .upper_margin = 3,
637 .lower_margin = 10,
638 .hsync_len = 72,
639 .vsync_len = 7,
640 .sync = 0x40000002,
641 .vmode = FB_VMODE_NONINTERLACED
642 } }, {
643 .bus = 0,
644 .addr = 0,
645 .pixfmt = IPU_PIX_FMT_RGB666,
646 .detect = NULL,
647 .enable = enable_rgb,
648 .mode = {
649 .name = "svga",
650 .refresh = 60,
651 .xres = 800,
652 .yres = 600,
653 .pixclock = 15385,
654 .left_margin = 220,
655 .right_margin = 40,
656 .upper_margin = 21,
657 .lower_margin = 7,
658 .hsync_len = 60,
659 .vsync_len = 10,
660 .sync = 0,
661 .vmode = FB_VMODE_NONINTERLACED
662 } }, {
663 .bus = 2,
664 .addr = 0x41,
665 .pixfmt = IPU_PIX_FMT_LVDS666,
666 .detect = detect_i2c,
667 .enable = enable_lvds,
668 .mode = {
669 .name = "amp1024x600",
670 .refresh = 60,
671 .xres = 1024,
672 .yres = 600,
673 .pixclock = 15385,
674 .left_margin = 220,
675 .right_margin = 40,
676 .upper_margin = 21,
677 .lower_margin = 7,
678 .hsync_len = 60,
679 .vsync_len = 10,
680 .sync = FB_SYNC_EXT,
681 .vmode = FB_VMODE_NONINTERLACED
682 } }, {
683 .bus = 0,
684 .addr = 0,
685 .pixfmt = IPU_PIX_FMT_LVDS666,
686 .detect = 0,
687 .enable = enable_lvds,
688 .mode = {
689 .name = "wvga-lvds",
690 .refresh = 57,
691 .xres = 800,
692 .yres = 480,
693 .pixclock = 15385,
694 .left_margin = 220,
695 .right_margin = 40,
696 .upper_margin = 21,
697 .lower_margin = 7,
698 .hsync_len = 60,
699 .vsync_len = 10,
700 .sync = FB_SYNC_EXT,
701 .vmode = FB_VMODE_NONINTERLACED
702 } }, {
703 .bus = 2,
704 .addr = 0x48,
705 .pixfmt = IPU_PIX_FMT_RGB666,
706 .detect = detect_i2c,
707 .enable = enable_rgb,
708 .mode = {
709 .name = "wvga-rgb",
710 .refresh = 57,
711 .xres = 800,
712 .yres = 480,
713 .pixclock = 37037,
714 .left_margin = 40,
715 .right_margin = 60,
716 .upper_margin = 10,
717 .lower_margin = 10,
718 .hsync_len = 20,
719 .vsync_len = 10,
720 .sync = 0,
721 .vmode = FB_VMODE_NONINTERLACED
722 } }, {
723 .bus = 0,
724 .addr = 0,
725 .pixfmt = IPU_PIX_FMT_RGB24,
726 .detect = NULL,
727 .enable = enable_rgb,
728 .mode = {
729 .name = "qvga",
730 .refresh = 60,
731 .xres = 320,
732 .yres = 240,
733 .pixclock = 37037,
734 .left_margin = 38,
735 .right_margin = 37,
736 .upper_margin = 16,
737 .lower_margin = 15,
738 .hsync_len = 30,
739 .vsync_len = 3,
740 .sync = 0,
741 .vmode = FB_VMODE_NONINTERLACED
742 } } };
743 size_t display_count = ARRAY_SIZE(displays);
744
745 int board_cfb_skip(void)
746 {
747 return NULL != getenv("novideo");
748 }
749
750 static void setup_display(void)
751 {
752 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
753 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
754 int reg;
755
756 enable_ipu_clock();
757 imx_setup_hdmi();
758 /* Turn on LDB0,IPU,IPU DI0 clocks */
759 reg = __raw_readl(&mxc_ccm->CCGR3);
760 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
761 writel(reg, &mxc_ccm->CCGR3);
762
763 /* set LDB0, LDB1 clk select to 011/011 */
764 reg = readl(&mxc_ccm->cs2cdr);
765 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
766 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
767 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
768 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
769 writel(reg, &mxc_ccm->cs2cdr);
770
771 reg = readl(&mxc_ccm->cscmr2);
772 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
773 writel(reg, &mxc_ccm->cscmr2);
774
775 reg = readl(&mxc_ccm->chsccdr);
776 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
777 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
778 writel(reg, &mxc_ccm->chsccdr);
779
780 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
781 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
782 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
783 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
784 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
785 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
786 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
787 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
788 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
789 writel(reg, &iomux->gpr[2]);
790
791 reg = readl(&iomux->gpr[3]);
792 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
793 |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
794 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
795 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
796 writel(reg, &iomux->gpr[3]);
797
798 /* backlights off until needed */
799 imx_iomux_v3_setup_multiple_pads(backlight_pads,
800 ARRAY_SIZE(backlight_pads));
801 gpio_direction_input(LVDS_BACKLIGHT_GP);
802 gpio_direction_input(RGB_BACKLIGHT_GP);
803 }
804 #endif
805
806 static iomux_v3_cfg_t const init_pads[] = {
807 /* SGTL5000 sys_mclk */
808 NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
809
810 /* J5 - Camera MCLK */
811 NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
812
813 /* wl1271 pads on nitrogen6x */
814 /* WL12XX_WL_IRQ_GP */
815 NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
816 /* WL12XX_WL_ENABLE_GP */
817 NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
818 /* WL12XX_BT_ENABLE_GP */
819 NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
820 /* USB otg power */
821 NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
822 NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
823 NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
824 NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
825 NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
826 };
827
828 #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
829
830 static unsigned gpios_out_low[] = {
831 /* Disable wl1271 */
832 IMX_GPIO_NR(6, 15), /* disable wireless */
833 IMX_GPIO_NR(6, 16), /* disable bluetooth */
834 IMX_GPIO_NR(3, 22), /* disable USB otg power */
835 IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */
836 IMX_GPIO_NR(1, 8), /* ov5642 reset */
837 };
838
839 static unsigned gpios_out_high[] = {
840 IMX_GPIO_NR(1, 6), /* ov5642 powerdown */
841 IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */
842 };
843
844 static void set_gpios(unsigned *p, int cnt, int val)
845 {
846 int i;
847
848 for (i = 0; i < cnt; i++)
849 gpio_direction_output(*p++, val);
850 }
851
852 int board_early_init_f(void)
853 {
854 setup_iomux_uart();
855
856 set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
857 set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
858 gpio_direction_input(WL12XX_WL_IRQ_GP);
859
860 imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
861 imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
862 setup_buttons();
863
864 #if defined(CONFIG_VIDEO_IPUV3)
865 setup_display();
866 #endif
867 return 0;
868 }
869
870 /*
871 * Do not overwrite the console
872 * Use always serial for U-Boot console
873 */
874 int overwrite_console(void)
875 {
876 return 1;
877 }
878
879 int board_init(void)
880 {
881 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
882
883 clrsetbits_le32(&iomuxc_regs->gpr[1],
884 IOMUXC_GPR1_OTG_ID_MASK,
885 IOMUXC_GPR1_OTG_ID_GPIO1);
886
887 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
888
889 /* address of boot parameters */
890 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
891
892 #ifdef CONFIG_MXC_SPI
893 setup_spi();
894 #endif
895 imx_iomux_v3_setup_multiple_pads(
896 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
897 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
898 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
899 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
900
901 #ifdef CONFIG_CMD_SATA
902 setup_sata();
903 #endif
904
905 return 0;
906 }
907
908 int checkboard(void)
909 {
910 if (gpio_get_value(WL12XX_WL_IRQ_GP))
911 puts("Board: Nitrogen6X\n");
912 else
913 puts("Board: SABRE Lite\n");
914
915 return 0;
916 }
917
918 struct button_key {
919 char const *name;
920 unsigned gpnum;
921 char ident;
922 };
923
924 static struct button_key const buttons[] = {
925 {"back", IMX_GPIO_NR(2, 2), 'B'},
926 {"home", IMX_GPIO_NR(2, 4), 'H'},
927 {"menu", IMX_GPIO_NR(2, 1), 'M'},
928 {"search", IMX_GPIO_NR(2, 3), 'S'},
929 {"volup", IMX_GPIO_NR(7, 13), 'V'},
930 {"voldown", IMX_GPIO_NR(4, 5), 'v'},
931 };
932
933 /*
934 * generate a null-terminated string containing the buttons pressed
935 * returns number of keys pressed
936 */
937 static int read_keys(char *buf)
938 {
939 int i, numpressed = 0;
940 for (i = 0; i < ARRAY_SIZE(buttons); i++) {
941 if (!gpio_get_value(buttons[i].gpnum))
942 buf[numpressed++] = buttons[i].ident;
943 }
944 buf[numpressed] = '\0';
945 return numpressed;
946 }
947
948 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
949 {
950 char envvalue[ARRAY_SIZE(buttons)+1];
951 int numpressed = read_keys(envvalue);
952 setenv("keybd", envvalue);
953 return numpressed == 0;
954 }
955
956 U_BOOT_CMD(
957 kbd, 1, 1, do_kbd,
958 "Tests for keypresses, sets 'keybd' environment variable",
959 "Returns 0 (true) to shell if key is pressed."
960 );
961
962 #ifdef CONFIG_PREBOOT
963 static char const kbd_magic_prefix[] = "key_magic";
964 static char const kbd_command_prefix[] = "key_cmd";
965
966 static void preboot_keys(void)
967 {
968 int numpressed;
969 char keypress[ARRAY_SIZE(buttons)+1];
970 numpressed = read_keys(keypress);
971 if (numpressed) {
972 char *kbd_magic_keys = getenv("magic_keys");
973 char *suffix;
974 /*
975 * loop over all magic keys
976 */
977 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
978 char *keys;
979 char magic[sizeof(kbd_magic_prefix) + 1];
980 sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
981 keys = getenv(magic);
982 if (keys) {
983 if (!strcmp(keys, keypress))
984 break;
985 }
986 }
987 if (*suffix) {
988 char cmd_name[sizeof(kbd_command_prefix) + 1];
989 char *cmd;
990 sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
991 cmd = getenv(cmd_name);
992 if (cmd) {
993 setenv("preboot", cmd);
994 return;
995 }
996 }
997 }
998 }
999 #endif
1000
1001 #ifdef CONFIG_CMD_BMODE
1002 static const struct boot_mode board_boot_modes[] = {
1003 /* 4 bit bus width */
1004 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
1005 {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
1006 {NULL, 0},
1007 };
1008 #endif
1009
1010 int misc_init_r(void)
1011 {
1012 #ifdef CONFIG_PREBOOT
1013 preboot_keys();
1014 #endif
1015
1016 #ifdef CONFIG_CMD_BMODE
1017 add_board_boot_modes(board_boot_modes);
1018 #endif
1019 return 0;
1020 }
"Das U-Boot" Source Tree