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git.ipfire.org Git - people/ms/u-boot.git/blob - board/canmb/canmb.c
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * SPDX-License-Identifier: GPL-2.0+
15 #if defined(CONFIG_MPC5200_DDR)
16 #include "mt46v16m16-75.h"
18 #include "mt48lc16m32s2-75.h"
21 DECLARE_GLOBAL_DATA_PTR
;
23 #ifndef CONFIG_SYS_RAMBOOT
24 static void sdram_start (int hi_addr
)
26 long hi_addr_bit
= hi_addr
? 0x01000000 : 0;
28 /* unlock mode register */
29 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000000 | hi_addr_bit
;
30 __asm__
volatile ("sync");
32 /* precharge all banks */
33 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
;
34 __asm__
volatile ("sync");
37 /* set mode register: extended mode */
38 *(vu_long
*)MPC5XXX_SDRAM_MODE
= SDRAM_EMODE
;
39 __asm__
volatile ("sync");
41 /* set mode register: reset DLL */
42 *(vu_long
*)MPC5XXX_SDRAM_MODE
= SDRAM_MODE
| 0x04000000;
43 __asm__
volatile ("sync");
46 /* precharge all banks */
47 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000002 | hi_addr_bit
;
48 __asm__
volatile ("sync");
51 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| 0x80000004 | hi_addr_bit
;
52 __asm__
volatile ("sync");
54 /* set mode register */
55 *(vu_long
*)MPC5XXX_SDRAM_MODE
= SDRAM_MODE
;
56 __asm__
volatile ("sync");
58 /* normal operation */
59 *(vu_long
*)MPC5XXX_SDRAM_CTRL
= SDRAM_CONTROL
| hi_addr_bit
;
60 __asm__
volatile ("sync");
65 * ATTENTION: Although partially referenced dram_init does NOT make real use
66 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
67 * is something else than 0x00000000.
74 #ifndef CONFIG_SYS_RAMBOOT
77 /* setup SDRAM chip selects */
78 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0x0000001e;/* 2G at 0x0 */
79 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= 0x80000000;/* disabled */
80 __asm__
volatile ("sync");
82 /* setup config registers */
83 *(vu_long
*)MPC5XXX_SDRAM_CONFIG1
= SDRAM_CONFIG1
;
84 *(vu_long
*)MPC5XXX_SDRAM_CONFIG2
= SDRAM_CONFIG2
;
85 __asm__
volatile ("sync");
89 *(vu_long
*)MPC5XXX_CDM_PORCFG
= SDRAM_TAPDELAY
;
90 __asm__
volatile ("sync");
93 /* find RAM size using SDRAM CS0 only */
95 test1
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x80000000);
97 test2
= get_ram_size((long *)CONFIG_SYS_SDRAM_BASE
, 0x80000000);
105 /* memory smaller than 1MB is impossible */
106 if (dramsize
< (1 << 20)) {
110 /* set SDRAM CS0 size according to the amount of RAM found */
112 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0x13 + __builtin_ffs(dramsize
>> 20) - 1;
114 *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
= 0; /* disabled */
117 /* let SDRAM CS1 start right after CS0 */
118 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
+ 0x0000001e;/* 2G */
120 /* find RAM size using SDRAM CS1 only */
123 test2
= test1
= get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE
+ dramsize
), 0x80000000);
126 test2
= get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE
+ dramsize
), 0x80000000);
135 /* memory smaller than 1MB is impossible */
136 if (dramsize2
< (1 << 20)) {
140 /* set SDRAM CS1 size according to the amount of RAM found */
142 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
143 | (0x13 + __builtin_ffs(dramsize2
>> 20) - 1);
145 *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
= dramsize
; /* disabled */
148 #else /* CONFIG_SYS_RAMBOOT */
150 /* retrieve size of memory connected to SDRAM CS0 */
151 dramsize
= *(vu_long
*)MPC5XXX_SDRAM_CS0CFG
& 0xFF;
152 if (dramsize
>= 0x13) {
153 dramsize
= (1 << (dramsize
- 0x13)) << 20;
158 /* retrieve size of memory connected to SDRAM CS1 */
159 dramsize2
= *(vu_long
*)MPC5XXX_SDRAM_CS1CFG
& 0xFF;
160 if (dramsize2
>= 0x13) {
161 dramsize2
= (1 << (dramsize2
- 0x13)) << 20;
166 #endif /* CONFIG_SYS_RAMBOOT */
168 gd
->ram_size
= dramsize
+ dramsize2
;
173 int checkboard (void)
175 puts ("Board: CANMB\n");
179 int board_early_init_r (void)
181 *(vu_long
*)MPC5XXX_BOOTCS_CFG
&= ~0x1; /* clear RO */
182 *(vu_long
*)MPC5XXX_BOOTCS_START
=
183 *(vu_long
*)MPC5XXX_CS0_START
= START_REG(CONFIG_SYS_FLASH_BASE
);
184 *(vu_long
*)MPC5XXX_BOOTCS_STOP
=
185 *(vu_long
*)MPC5XXX_CS0_STOP
= STOP_REG(CONFIG_SYS_FLASH_BASE
, CONFIG_SYS_FLASH_SIZE
);