2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6ul_pins.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/mxc_i2c.h>
20 #include <fsl_esdhc.h>
26 #include <usb/ehci-ci.h>
28 DECLARE_GLOBAL_DATA_PTR
;
30 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
32 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
34 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
36 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
40 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
44 PAD_CTL_SPEED_HIGH | \
45 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
47 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
48 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
50 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
52 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
53 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
55 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
56 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
57 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
60 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
62 static struct i2c_pads_info i2c_pad_info1
= {
64 .i2c_mode
= MX6_PAD_GPIO1_IO02__I2C1_SCL
| PC
,
65 .gpio_mode
= MX6_PAD_GPIO1_IO02__GPIO1_IO02
| PC
,
66 .gp
= IMX_GPIO_NR(1, 2),
69 .i2c_mode
= MX6_PAD_GPIO1_IO03__I2C1_SDA
| PC
,
70 .gpio_mode
= MX6_PAD_GPIO1_IO03__GPIO1_IO03
| PC
,
71 .gp
= IMX_GPIO_NR(1, 3),
75 static struct i2c_pads_info i2c_pad_info2
= {
77 .i2c_mode
= MX6_PAD_GPIO1_IO00__I2C2_SCL
| PC
,
78 .gpio_mode
= MX6_PAD_GPIO1_IO00__GPIO1_IO00
| PC
,
79 .gp
= IMX_GPIO_NR(1, 0),
82 .i2c_mode
= MX6_PAD_GPIO1_IO01__I2C2_SDA
| PC
,
83 .gpio_mode
= MX6_PAD_GPIO1_IO01__GPIO1_IO01
| PC
,
84 .gp
= IMX_GPIO_NR(1, 1),
88 static struct i2c_pads_info i2c_pad_info4
= {
90 .i2c_mode
= MX6_PAD_UART2_TX_DATA__I2C4_SCL
| PC
,
91 .gpio_mode
= MX6_PAD_UART2_TX_DATA__GPIO1_IO20
| PC
,
92 .gp
= IMX_GPIO_NR(1, 20),
95 .i2c_mode
= MX6_PAD_UART2_RX_DATA__I2C4_SDA
| PC
,
96 .gpio_mode
= MX6_PAD_UART2_RX_DATA__GPIO1_IO21
| PC
,
97 .gp
= IMX_GPIO_NR(1, 21),
103 gd
->ram_size
= get_ram_size((void *)PHYS_SDRAM
, PHYS_SDRAM_SIZE
);
108 static iomux_v3_cfg_t
const uart1_pads
[] = {
109 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
110 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
113 static iomux_v3_cfg_t
const uart4_pads
[] = {
114 MX6_PAD_UART4_TX_DATA__UART4_DCE_TX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
115 MX6_PAD_UART4_RX_DATA__UART4_DCE_RX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
118 static iomux_v3_cfg_t
const uart5_pads
[] = {
119 MX6_PAD_GPIO1_IO04__UART5_DCE_TX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
120 MX6_PAD_GPIO1_IO05__UART5_DCE_RX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
121 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS
| MUX_PAD_CTRL(UART_PAD_CTRL
),
122 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS
| MUX_PAD_CTRL(UART_PAD_CTRL
),
125 static iomux_v3_cfg_t
const uart8_pads
[] = {
126 MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
127 MX6_PAD_ENET2_TX_EN__UART8_DCE_RX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
128 MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS
| MUX_PAD_CTRL(UART_PAD_CTRL
),
129 MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS
| MUX_PAD_CTRL(UART_PAD_CTRL
),
132 static void setup_iomux_uart(void)
134 imx_iomux_v3_setup_multiple_pads(uart1_pads
, ARRAY_SIZE(uart1_pads
));
135 imx_iomux_v3_setup_multiple_pads(uart4_pads
, ARRAY_SIZE(uart4_pads
));
136 imx_iomux_v3_setup_multiple_pads(uart5_pads
, ARRAY_SIZE(uart5_pads
));
137 imx_iomux_v3_setup_multiple_pads(uart8_pads
, ARRAY_SIZE(uart8_pads
));
141 static iomux_v3_cfg_t
const usdhc2_pads
[] = {
142 MX6_PAD_NAND_RE_B__USDHC2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
143 MX6_PAD_NAND_WE_B__USDHC2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
144 MX6_PAD_NAND_DATA00__USDHC2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
145 MX6_PAD_NAND_DATA01__USDHC2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
146 MX6_PAD_NAND_DATA02__USDHC2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
147 MX6_PAD_NAND_DATA03__USDHC2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
148 MX6_PAD_NAND_DATA04__USDHC2_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
149 MX6_PAD_NAND_DATA05__USDHC2_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
150 MX6_PAD_NAND_DATA06__USDHC2_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
151 MX6_PAD_NAND_DATA07__USDHC2_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
156 MX6_PAD_NAND_ALE__USDHC2_RESET_B
| MUX_PAD_CTRL(NO_PAD_CTRL
),
159 static struct fsl_esdhc_cfg usdhc_cfg
= {
160 .esdhc_base
= USDHC2_BASE_ADDR
,
164 #define USDHC2_PWR_GPIO IMX_GPIO_NR(1, 9)
166 int board_mmc_getcd(struct mmc
*mmc
)
168 /* eMMC is always present */
172 int board_mmc_init(bd_t
*bis
)
174 imx_iomux_v3_setup_multiple_pads(usdhc2_pads
, ARRAY_SIZE(usdhc2_pads
));
176 usdhc_cfg
.sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
178 return fsl_esdhc_initialize(bis
, &usdhc_cfg
);
181 #define USB_OTHERREGS_OFFSET 0x800
182 #define UCTRL_PWR_POL (1 << 9)
184 static iomux_v3_cfg_t
const usb_otg_pads
[] = {
186 MX6_PAD_SD1_CMD__USB_OTG1_PWR
| MUX_PAD_CTRL(NO_PAD_CTRL
),
187 MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID
| MUX_PAD_CTRL(OTGID_PAD_CTRL
),
189 MX6_PAD_SD1_DATA1__USB_OTG2_PWR
| MUX_PAD_CTRL(NO_PAD_CTRL
),
190 MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID
| MUX_PAD_CTRL(OTGID_PAD_CTRL
),
193 static void setup_usb(void)
195 imx_iomux_v3_setup_multiple_pads(usb_otg_pads
,
196 ARRAY_SIZE(usb_otg_pads
));
199 int board_usb_phy_mode(int port
)
202 return USB_INIT_HOST
;
204 return usb_phy_mode(port
);
207 int board_ehci_hcd_init(int port
)
214 usbnc_usb_ctrl
= (u32
*)(USB_BASE_ADDR
+ USB_OTHERREGS_OFFSET
+
217 /* Set Power polarity */
218 setbits_le32(usbnc_usb_ctrl
, UCTRL_PWR_POL
);
223 static iomux_v3_cfg_t
const fec1_pads
[] = {
224 MX6_PAD_GPIO1_IO06__ENET1_MDIO
| MUX_PAD_CTRL(MDIO_PAD_CTRL
),
225 MX6_PAD_GPIO1_IO07__ENET1_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
226 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
227 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
228 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
229 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1
| MUX_PAD_CTRL(ENET_CLK_PAD_CTRL
),
230 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
231 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
232 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
233 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
236 MX6_PAD_CSI_MCLK__GPIO4_IO17
| MUX_PAD_CTRL(NO_PAD_CTRL
),
237 /* ENET1 interrupt */
238 MX6_PAD_CSI_PIXCLK__GPIO4_IO18
| MUX_PAD_CTRL(NO_PAD_CTRL
),
241 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(4, 17)
243 int board_eth_init(bd_t
*bis
)
247 imx_iomux_v3_setup_multiple_pads(fec1_pads
, ARRAY_SIZE(fec1_pads
));
249 /* Reset LAN8742 PHY */
250 ret
= gpio_request(ENET_PHY_RESET_GPIO
, "phy-reset");
252 gpio_direction_output(ENET_PHY_RESET_GPIO
, 0);
254 gpio_set_value(ENET_PHY_RESET_GPIO
, 1);
257 return cpu_eth_init(bis
);
260 static int setup_fec(int fec_id
)
262 struct iomuxc
*const iomuxc_regs
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
266 * Use 50M anatop loopback REF_CLK1 for ENET1,
267 * clear gpr1[13], set gpr1[17].
269 clrsetbits_le32(&iomuxc_regs
->gpr
[1], IOMUX_GPR1_FEC1_MASK
,
270 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK
);
272 ret
= enable_fec_anatop_clock(fec_id
, ENET_50MHZ
);
281 int board_phy_config(struct phy_device
*phydev
)
283 if (phydev
->drv
->config
)
284 phydev
->drv
->config(phydev
);
289 int board_early_init_f(void)
298 /* Address of boot parameters */
299 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
301 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info1
);
302 setup_i2c(1, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info2
);
303 setup_i2c(3, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info4
);
305 setup_fec(CONFIG_FEC_ENET_DEV
);
312 static const struct boot_mode board_boot_modes
[] = {
313 /* 8 bit bus width */
314 {"emmc", MAKE_CFGVAL(0x60, 0x28, 0x00, 0x00)},
318 int board_late_init(void)
320 add_board_boot_modes(board_boot_modes
);
321 env_set("board_name", "xpress");
328 puts("Board: CCV-EVA xPress\n");