board/cds/mpc8548cds/init.S

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * Copyright 2002,2003, Motorola Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <ppc_asm.tmpl>
  25 #include <ppc_defs.h>
  26 #include <asm/cache.h>
  27 #include <asm/mmu.h>
  28 #include <config.h>
  29 #include <mpc85xx.h>
  30
  31
  32 /*
  33  * TLB0 and TLB1 Entries
  34  *
  35  * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
  36  * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
  37  * these TLB entries are established.
  38  *
  39  * The TLB entries for DDR are dynamically setup in spd_sdram()
  40  * and use TLB1 Entries 8 through 15 as needed according to the
  41  * size of DDR memory.
  42  *
  43  * MAS0: tlbsel, esel, nv
  44  * MAS1: valid, iprot, tid, ts, tsize
  45  * MAS2: epn, sharen, x0, x1, w, i, m, g, e
  46  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  47  */
  48
  49 #define entry_start \
  50         mflr    r1      ;       \
  51         bl      0f      ;
  52
  53 #define entry_end \
  54 0:      mflr    r0      ;       \
  55         mtlr    r1      ;       \
  56         blr             ;
  57
  58
  59         .section        .bootpg, "ax"
  60         .globl  tlb1_entry
  61 tlb1_entry:
  62         entry_start
  63
  64         /*
  65          * Number of TLB0 and TLB1 entries in the following table
  66          */
  67         .long (2f-1f)/16
  68
  69 1:
  70 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
  71         /*
  72          * TLB0         4K      Non-cacheable, guarded
  73          * 0xff700000   4K      Initial CCSRBAR mapping
  74          *
  75          * This ends up at a TLB0 Index==0 entry, and must not collide
  76          * with other TLB0 Entries.
  77          */
  78         .long TLB1_MAS0(0, 0, 0)
  79         .long TLB1_MAS1(1, 0, 0, 0, 0)
  80         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
  81         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
  82 #else
  83 #error("Update the number of table entries in tlb1_entry")
  84 #endif
  85
  86         /*
  87          * TLB0         16K     Cacheable, non-guarded
  88          * 0xd001_0000  16K     Temporary Global data for initialization
  89          *
  90          * Use four 4K TLB0 entries.  These entries must be cacheable
  91          * as they provide the bootstrap memory before the memory
  92          * controler and real memory have been configured.
  93          *
  94          * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
  95          * and must not collide with other TLB0 entries.
  96          */
  97         .long TLB1_MAS0(0, 0, 0)
  98         .long TLB1_MAS1(1, 0, 0, 0, 0)
  99         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
 100                         0,0,0,0,0,0,0,0)
 101         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
 102                         0,0,0,0,0,1,0,1,0,1)
 103
 104         .long TLB1_MAS0(0, 0, 0)
 105         .long TLB1_MAS1(1, 0, 0, 0, 0)
 106         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
 107                         0,0,0,0,0,0,0,0)
 108         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
 109                         0,0,0,0,0,1,0,1,0,1)
 110
 111         .long TLB1_MAS0(0, 0, 0)
 112         .long TLB1_MAS1(1, 0, 0, 0, 0)
 113         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 114                         0,0,0,0,0,0,0,0)
 115         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 116                         0,0,0,0,0,1,0,1,0,1)
 117
 118         .long TLB1_MAS0(0, 0, 0)
 119         .long TLB1_MAS1(1, 0, 0, 0, 0)
 120         .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 121                         0,0,0,0,0,0,0,0)
 122         .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 123                         0,0,0,0,0,1,0,1,0,1)
 124
 125
 126         /*
 127          * TLB 0:       16M     Non-cacheable, guarded
 128          * 0xff000000   16M     FLASH
 129          * Out of reset this entry is only 4K.
 130          */
 131         .long TLB1_MAS0(1, 0, 0)
 132         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
 133         .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
 134         .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
 135
 136         /*
 137          * TLB 1:       256M    Non-cacheable, guarded
 138          * 0x80000000   256M    PCI1 MEM
 139          */
 140         .long TLB1_MAS0(1, 1, 0)
 141         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 142         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
 143         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
 144
 145         /*
 146          * TLB 2:       256M    Non-cacheable, guarded
 147          * 0x90000000   256M    PCI2 MEM
 148          */
 149         .long TLB1_MAS0(1, 2, 0)
 150         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
 151         .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE),
 152                         0,0,0,0,1,0,1,0)
 153         .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE),
 154                         0,0,0,0,0,1,0,1,0,1)
 155
 156         /*
 157          * TLB 3:       1GB     Non-cacheable, guarded
 158          * 0xa0000000   256M    PEX MEM First half
 159          * 0xb0000000   256M    PEX MEM Second half
 160          * 0xc0000000   256M    Rapid IO MEM First half
 161          * 0xd0000000   256M    Rapid IO MEM Second half
 162          */
 163         .long TLB1_MAS0(1, 3, 0)
 164         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1GB)
 165         .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
 166         .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
 167
 168         /*
 169          * TLB 4:       Reserved for future usage
 170          */
 171
 172         /*
 173          * TLB 5:       64M     Non-cacheable, guarded
 174          * 0xe000_0000  1M      CCSRBAR
 175          * 0xe200_0000  8M      PCI1 IO
 176          * 0xe280_0000  8M      PCI2 IO
 177          * 0xe300_0000  16M     PEX IO
 178          */
 179         .long TLB1_MAS0(1, 5, 0)
 180         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 181         .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
 182         .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
 183
 184         /*
 185          * TLB 6:       64M     Cacheable, non-guarded
 186          * 0xf000_0000  64M     LBC SDRAM
 187          */
 188         .long TLB1_MAS0(1, 6, 0)
 189         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
 190         .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
 191         .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
 192
 193         /*
 194          * TLB 7:       1M      Non-cacheable, guarded
 195          * 0xf8000000   1M      CADMUS registers
 196          */
 197         .long TLB1_MAS0(1, 7, 0)
 198         .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
 199         .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
 200         .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
 201 2:
 202         entry_end
 203
 204 /*
 205  * LAW(Local Access Window) configuration:
 206  *
 207  * 0x0000_0000     0x7fff_ffff     DDR                     2G
 208  * 0x8000_0000     0x8fff_ffff     PCI1 MEM                256M
 209  * 0x9000_0000     0x9fff_ffff     PCI2 MEM                256M
 210  * 0xa000_0000     0xbfff_ffff     PEX MEM                 512M
 211  * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
 212  * 0xe000_0000     0xe000_ffff     CCSR                    1M
 213  * 0xe200_0000     0xe27f_ffff     PCI1 IO                 8M
 214  * 0xe280_0000     0xe2ff_ffff     PCI2 IO                 8M
 215  * 0xe300_0000     0xe3ff_ffff     PEX IO                  16M
 216  * 0xf000_0000     0xf3ff_ffff     SDRAM                   64M
 217  * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
 218  * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
 219  * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
 220  *
 221  * Notes:
 222  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
 223  *    If flash is 8M at default position (last 8M), no LAW needed.
 224  *
 225  * The defines below are 1-off of the actual LAWAR0 usage.
 226  * So LAWAR3 define uses the LAWAR4 register in the ECM.
 227  */
 228
 229 #define LAWBAR0 0
 230 #define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
 231
 232 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
 233 #define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
 234
 235 #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
 236 #define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
 237
 238 #define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
 239 #define LAWAR3  (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 240
 241 #define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
 242 #define LAWAR4  (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M))
 243
 244 /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 245 #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
 246 #define LAWAR5  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
 247
 248 #define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
 249 #define LAWAR6  (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
 250
 251 #define LAWBAR7 ((CFG_PEX_IO_BASE>>12) & 0xfffff)
 252 #define LAWAR7  (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
 253
 254 #define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
 255 #define LAWAR8  (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
 256
 257         .section .bootpg, "ax"
 258         .globl  law_entry
 259
 260 law_entry:
 261         entry_start
 262         .long (4f-3f)/8
 263 3:
 264         .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
 265         .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7
 266         .long LAWBAR8,LAWAR8
 267 4:
 268         entry_end