board/cm_t35/cm_t35.c

   1 /*
   2  * (C) Copyright 2010
   3  * CompuLab, Ltd. <www.compulab.co.il>
   4  *
   5  * Author: Mike Rapoport <mike@compulab.co.il>
   6  *
   7  * Derived from omap3evm and Beagle Board by
   8  *      Manikandan Pillai <mani.pillai@ti.com>
   9  *      Richard Woodruff <r-woodruff2@ti.com>
  10  *      Syed Mohammed Khasim <x0khasim@ti.com>
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #include <common.h>
  32 #include <netdev.h>
  33 #include <net.h>
  34 #include <i2c.h>
  35 #include <twl4030.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/arch/mem.h>
  39 #include <asm/arch/mux.h>
  40 #include <asm/arch/mmc_host_def.h>
  41 #include <asm/arch/sys_proto.h>
  42 #include <asm/mach-types.h>
  43
  44 const omap3_sysinfo sysinfo = {
  45         DDR_DISCRETE,
  46         "CM-T35 board",
  47         "NAND",
  48 };
  49
  50 static u32 gpmc_net_config[GPMC_MAX_REG] = {
  51         NET_GPMC_CONFIG1,
  52         NET_GPMC_CONFIG2,
  53         NET_GPMC_CONFIG3,
  54         NET_GPMC_CONFIG4,
  55         NET_GPMC_CONFIG5,
  56         NET_GPMC_CONFIG6,
  57         0
  58 };
  59
  60 static u32 gpmc_nand_config[GPMC_MAX_REG] = {
  61         SMNAND_GPMC_CONFIG1,
  62         SMNAND_GPMC_CONFIG2,
  63         SMNAND_GPMC_CONFIG3,
  64         SMNAND_GPMC_CONFIG4,
  65         SMNAND_GPMC_CONFIG5,
  66         SMNAND_GPMC_CONFIG6,
  67         0,
  68 };
  69
  70 /*
  71  * Routine: board_init
  72  * Description: Early hardware init.
  73  */
  74 int board_init(void)
  75 {
  76         DECLARE_GLOBAL_DATA_PTR;
  77
  78         gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  79
  80         enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
  81                               CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
  82
  83         /* board id for Linux */
  84         gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
  85         /* boot param addr */
  86         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  87
  88         return 0;
  89 }
  90
  91 /*
  92  * Routine: misc_init_r
  93  * Description: Init I2C and display die ID
  94  */
  95 int misc_init_r(void)
  96 {
  97 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
  98         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  99 #endif
 100
 101         dieid_num_r();
 102
 103         return 0;
 104 }
 105
 106 /*
 107  * Routine: set_muxconf_regs
 108  * Description: Setting up the configuration Mux registers specific to the
 109  *              hardware. Many pins need to be moved from protect to primary
 110  *              mode.
 111  */
 112 void set_muxconf_regs(void)
 113 {
 114         /* SDRC */
 115         MUX_VAL(CP(SDRC_D0),            (IEN  | PTD | DIS | M0)); /*SDRC_D0*/
 116         MUX_VAL(CP(SDRC_D1),            (IEN  | PTD | DIS | M0)); /*SDRC_D1*/
 117         MUX_VAL(CP(SDRC_D2),            (IEN  | PTD | DIS | M0)); /*SDRC_D2*/
 118         MUX_VAL(CP(SDRC_D3),            (IEN  | PTD | DIS | M0)); /*SDRC_D3*/
 119         MUX_VAL(CP(SDRC_D4),            (IEN  | PTD | DIS | M0)); /*SDRC_D4*/
 120         MUX_VAL(CP(SDRC_D5),            (IEN  | PTD | DIS | M0)); /*SDRC_D5*/
 121         MUX_VAL(CP(SDRC_D6),            (IEN  | PTD | DIS | M0)); /*SDRC_D6*/
 122         MUX_VAL(CP(SDRC_D7),            (IEN  | PTD | DIS | M0)); /*SDRC_D7*/
 123         MUX_VAL(CP(SDRC_D8),            (IEN  | PTD | DIS | M0)); /*SDRC_D8*/
 124         MUX_VAL(CP(SDRC_D9),            (IEN  | PTD | DIS | M0)); /*SDRC_D9*/
 125         MUX_VAL(CP(SDRC_D10),           (IEN  | PTD | DIS | M0)); /*SDRC_D10*/
 126         MUX_VAL(CP(SDRC_D11),           (IEN  | PTD | DIS | M0)); /*SDRC_D11*/
 127         MUX_VAL(CP(SDRC_D12),           (IEN  | PTD | DIS | M0)); /*SDRC_D12*/
 128         MUX_VAL(CP(SDRC_D13),           (IEN  | PTD | DIS | M0)); /*SDRC_D13*/
 129         MUX_VAL(CP(SDRC_D14),           (IEN  | PTD | DIS | M0)); /*SDRC_D14*/
 130         MUX_VAL(CP(SDRC_D15),           (IEN  | PTD | DIS | M0)); /*SDRC_D15*/
 131         MUX_VAL(CP(SDRC_D16),           (IEN  | PTD | DIS | M0)); /*SDRC_D16*/
 132         MUX_VAL(CP(SDRC_D17),           (IEN  | PTD | DIS | M0)); /*SDRC_D17*/
 133         MUX_VAL(CP(SDRC_D18),           (IEN  | PTD | DIS | M0)); /*SDRC_D18*/
 134         MUX_VAL(CP(SDRC_D19),           (IEN  | PTD | DIS | M0)); /*SDRC_D19*/
 135         MUX_VAL(CP(SDRC_D20),           (IEN  | PTD | DIS | M0)); /*SDRC_D20*/
 136         MUX_VAL(CP(SDRC_D21),           (IEN  | PTD | DIS | M0)); /*SDRC_D21*/
 137         MUX_VAL(CP(SDRC_D22),           (IEN  | PTD | DIS | M0)); /*SDRC_D22*/
 138         MUX_VAL(CP(SDRC_D23),           (IEN  | PTD | DIS | M0)); /*SDRC_D23*/
 139         MUX_VAL(CP(SDRC_D24),           (IEN  | PTD | DIS | M0)); /*SDRC_D24*/
 140         MUX_VAL(CP(SDRC_D25),           (IEN  | PTD | DIS | M0)); /*SDRC_D25*/
 141         MUX_VAL(CP(SDRC_D26),           (IEN  | PTD | DIS | M0)); /*SDRC_D26*/
 142         MUX_VAL(CP(SDRC_D27),           (IEN  | PTD | DIS | M0)); /*SDRC_D27*/
 143         MUX_VAL(CP(SDRC_D28),           (IEN  | PTD | DIS | M0)); /*SDRC_D28*/
 144         MUX_VAL(CP(SDRC_D29),           (IEN  | PTD | DIS | M0)); /*SDRC_D29*/
 145         MUX_VAL(CP(SDRC_D30),           (IEN  | PTD | DIS | M0)); /*SDRC_D30*/
 146         MUX_VAL(CP(SDRC_D31),           (IEN  | PTD | DIS | M0)); /*SDRC_D31*/
 147         MUX_VAL(CP(SDRC_CLK),           (IEN  | PTD | DIS | M0)); /*SDRC_CLK*/
 148         MUX_VAL(CP(SDRC_DQS0),          (IEN  | PTD | DIS | M0)); /*SDRC_DQS0*/
 149         MUX_VAL(CP(SDRC_DQS1),          (IEN  | PTD | DIS | M0)); /*SDRC_DQS1*/
 150         MUX_VAL(CP(SDRC_DQS2),          (IEN  | PTD | DIS | M0)); /*SDRC_DQS2*/
 151         MUX_VAL(CP(SDRC_DQS3),          (IEN  | PTD | DIS | M0)); /*SDRC_DQS3*/
 152         MUX_VAL(CP(SDRC_CKE0),          (IDIS | PTU | EN  | M0)); /*SDRC_CKE0*/
 153         MUX_VAL(CP(SDRC_CKE1),          (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
 154
 155         /* GPMC */
 156         MUX_VAL(CP(GPMC_A1),            (IDIS | PTU | EN  | M0)); /*GPMC_A1*/
 157         MUX_VAL(CP(GPMC_A2),            (IDIS | PTU | EN  | M0)); /*GPMC_A2*/
 158         MUX_VAL(CP(GPMC_A3),            (IDIS | PTU | EN  | M0)); /*GPMC_A3*/
 159         MUX_VAL(CP(GPMC_A4),            (IDIS | PTU | EN  | M0)); /*GPMC_A4*/
 160         MUX_VAL(CP(GPMC_A5),            (IDIS | PTU | EN  | M0)); /*GPMC_A5*/
 161         MUX_VAL(CP(GPMC_A6),            (IDIS | PTU | EN  | M0)); /*GPMC_A6*/
 162         MUX_VAL(CP(GPMC_A7),            (IDIS | PTU | EN  | M0)); /*GPMC_A7*/
 163         MUX_VAL(CP(GPMC_A8),            (IDIS | PTU | EN  | M0)); /*GPMC_A8*/
 164         MUX_VAL(CP(GPMC_A9),            (IDIS | PTU | EN  | M0)); /*GPMC_A9*/
 165         MUX_VAL(CP(GPMC_A10),           (IDIS | PTU | EN  | M0)); /*GPMC_A10*/
 166         MUX_VAL(CP(GPMC_D0),            (IEN  | PTU | EN  | M0)); /*GPMC_D0*/
 167         MUX_VAL(CP(GPMC_D1),            (IEN  | PTU | EN  | M0)); /*GPMC_D1*/
 168         MUX_VAL(CP(GPMC_D2),            (IEN  | PTU | EN  | M0)); /*GPMC_D2*/
 169         MUX_VAL(CP(GPMC_D3),            (IEN  | PTU | EN  | M0)); /*GPMC_D3*/
 170         MUX_VAL(CP(GPMC_D4),            (IEN  | PTU | EN  | M0)); /*GPMC_D4*/
 171         MUX_VAL(CP(GPMC_D5),            (IEN  | PTU | EN  | M0)); /*GPMC_D5*/
 172         MUX_VAL(CP(GPMC_D6),            (IEN  | PTU | EN  | M0)); /*GPMC_D6*/
 173         MUX_VAL(CP(GPMC_D7),            (IEN  | PTU | EN  | M0)); /*GPMC_D7*/
 174         MUX_VAL(CP(GPMC_D8),            (IEN  | PTU | EN  | M0)); /*GPMC_D8*/
 175         MUX_VAL(CP(GPMC_D9),            (IEN  | PTU | EN  | M0)); /*GPMC_D9*/
 176         MUX_VAL(CP(GPMC_D10),           (IEN  | PTU | EN  | M0)); /*GPMC_D10*/
 177         MUX_VAL(CP(GPMC_D11),           (IEN  | PTU | EN  | M0)); /*GPMC_D11*/
 178         MUX_VAL(CP(GPMC_D12),           (IEN  | PTU | EN  | M0)); /*GPMC_D12*/
 179         MUX_VAL(CP(GPMC_D13),           (IEN  | PTU | EN  | M0)); /*GPMC_D13*/
 180         MUX_VAL(CP(GPMC_D14),           (IEN  | PTU | EN  | M0)); /*GPMC_D14*/
 181         MUX_VAL(CP(GPMC_D15),           (IEN  | PTU | EN  | M0)); /*GPMC_D15*/
 182         MUX_VAL(CP(GPMC_NCS0),          (IDIS | PTU | EN  | M0)); /*GPMC_nCS0*/
 183
 184         /* SB-T35 Ethernet */
 185         MUX_VAL(CP(GPMC_NCS4),          (IEN  | PTU | EN  | M0)); /*GPMC_nCS4*/
 186
 187         /* CM-T35 Ethernet */
 188         MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
 189         MUX_VAL(CP(GPMC_CLK),           (IEN  | PTD | DIS | M4)); /*GPIO_59*/
 190         MUX_VAL(CP(GPMC_NADV_ALE),      (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
 191         MUX_VAL(CP(GPMC_NOE),           (IDIS | PTD | DIS | M0)); /*nOE*/
 192         MUX_VAL(CP(GPMC_NWE),           (IDIS | PTD | DIS | M0)); /*nWE*/
 193         MUX_VAL(CP(GPMC_NBE0_CLE),      (IDIS | PTU | EN  | M0)); /*nBE0_CLE*/
 194         MUX_VAL(CP(GPMC_NBE1),          (IDIS | PTD | DIS | M4)); /*GPIO_61*/
 195         MUX_VAL(CP(GPMC_NWP),           (IEN  | PTD | DIS | M0)); /*nWP*/
 196         MUX_VAL(CP(GPMC_WAIT0),         (IEN  | PTU | EN  | M0)); /*WAIT0*/
 197
 198         /* DSS */
 199         MUX_VAL(CP(DSS_PCLK),           (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
 200         MUX_VAL(CP(DSS_HSYNC),          (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
 201         MUX_VAL(CP(DSS_VSYNC),          (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
 202         MUX_VAL(CP(DSS_ACBIAS),         (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
 203         MUX_VAL(CP(DSS_DATA0),          (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
 204         MUX_VAL(CP(DSS_DATA1),          (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
 205         MUX_VAL(CP(DSS_DATA2),          (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
 206         MUX_VAL(CP(DSS_DATA3),          (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
 207         MUX_VAL(CP(DSS_DATA4),          (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
 208         MUX_VAL(CP(DSS_DATA5),          (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
 209         MUX_VAL(CP(DSS_DATA6),          (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
 210         MUX_VAL(CP(DSS_DATA7),          (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
 211         MUX_VAL(CP(DSS_DATA8),          (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
 212         MUX_VAL(CP(DSS_DATA9),          (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
 213         MUX_VAL(CP(DSS_DATA10),         (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
 214         MUX_VAL(CP(DSS_DATA11),         (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
 215         MUX_VAL(CP(DSS_DATA12),         (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
 216         MUX_VAL(CP(DSS_DATA13),         (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
 217         MUX_VAL(CP(DSS_DATA14),         (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
 218         MUX_VAL(CP(DSS_DATA15),         (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
 219         MUX_VAL(CP(DSS_DATA16),         (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
 220         MUX_VAL(CP(DSS_DATA17),         (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
 221         MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
 222         MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
 223         MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
 224         MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
 225         MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
 226         MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
 227
 228         /* serial interface */
 229         MUX_VAL(CP(UART3_RX_IRRX),      (IEN  | PTD | DIS | M0)); /*UART3_RX*/
 230         MUX_VAL(CP(UART3_TX_IRTX),      (IDIS | PTD | DIS | M0)); /*UART3_TX*/
 231
 232         /* mUSB */
 233         MUX_VAL(CP(HSUSB0_CLK),         (IEN  | PTD | DIS | M0)); /*HSUSB0_CLK*/
 234         MUX_VAL(CP(HSUSB0_STP),         (IDIS | PTU | EN  | M0)); /*HSUSB0_STP*/
 235         MUX_VAL(CP(HSUSB0_DIR),         (IEN  | PTD | DIS | M0)); /*HSUSB0_DIR*/
 236         MUX_VAL(CP(HSUSB0_NXT),         (IEN  | PTD | DIS | M0)); /*HSUSB0_NXT*/
 237         MUX_VAL(CP(HSUSB0_DATA0),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA0*/
 238         MUX_VAL(CP(HSUSB0_DATA1),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA1*/
 239         MUX_VAL(CP(HSUSB0_DATA2),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA2*/
 240         MUX_VAL(CP(HSUSB0_DATA3),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA3*/
 241         MUX_VAL(CP(HSUSB0_DATA4),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA4*/
 242         MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA5*/
 243         MUX_VAL(CP(HSUSB0_DATA6),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA6*/
 244         MUX_VAL(CP(HSUSB0_DATA7),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA7*/
 245
 246         /* I2C1 */
 247         MUX_VAL(CP(I2C1_SCL),           (IEN  | PTU | EN  | M0)); /*I2C1_SCL*/
 248         MUX_VAL(CP(I2C1_SDA),           (IEN  | PTU | EN  | M0)); /*I2C1_SDA*/
 249
 250         /* control and debug */
 251         MUX_VAL(CP(SYS_32K),            (IEN  | PTD | DIS | M0)); /*SYS_32K*/
 252         MUX_VAL(CP(SYS_CLKREQ),         (IEN  | PTD | DIS | M0)); /*SYS_CLKREQ*/
 253         MUX_VAL(CP(SYS_NIRQ),           (IEN  | PTU | EN  | M0)); /*SYS_nIRQ*/
 254         MUX_VAL(CP(SYS_OFF_MODE),       (IEN  | PTD | DIS | M0)); /*OFF_MODE*/
 255         MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTD | DIS | M0)); /*CLKOUT1*/
 256         MUX_VAL(CP(SYS_CLKOUT2),        (IDIS | PTD | DIS | M4)); /*green LED*/
 257         MUX_VAL(CP(JTAG_nTRST),         (IEN  | PTD | DIS | M0)); /*JTAG_nTRST*/
 258         MUX_VAL(CP(JTAG_TCK),           (IEN  | PTD | DIS | M0)); /*JTAG_TCK*/
 259         MUX_VAL(CP(JTAG_TMS),           (IEN  | PTD | DIS | M0)); /*JTAG_TMS*/
 260         MUX_VAL(CP(JTAG_TDI),           (IEN  | PTD | DIS | M0)); /*JTAG_TDI*/
 261 }
 262
 263 #ifdef CONFIG_GENERIC_MMC
 264 int board_mmc_init(bd_t *bis)
 265 {
 266         return omap_mmc_init(0);
 267 }
 268 #endif
 269
 270 /*
 271  * Routine: setup_net_chip_gmpc
 272  * Description: Setting up the configuration GPMC registers specific to the
 273  *              Ethernet hardware.
 274  */
 275 static void setup_net_chip_gmpc(void)
 276 {
 277         struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 278
 279         enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
 280                               CM_T35_SMC911X_BASE, GPMC_SIZE_16M);
 281         enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
 282                               SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
 283
 284         /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 285         writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
 286
 287         /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
 288         writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
 289
 290         /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
 291         writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
 292                 &ctrl_base->gpmc_nadv_ale);
 293 }
 294
 295 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
 296 /*
 297  * Routine: reset_net_chip
 298  * Description: reset the Ethernet controller via TPS65930 GPIO
 299  */
 300 static void reset_net_chip(void)
 301 {
 302         /* Set GPIO1 of TPS65930 as output */
 303         twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
 304                              TWL4030_BASEADD_GPIO+0x03);
 305         /* Send a pulse on the GPIO pin */
 306         twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
 307                              TWL4030_BASEADD_GPIO+0x0C);
 308         udelay(1);
 309         twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
 310                              TWL4030_BASEADD_GPIO+0x09);
 311         udelay(1);
 312         twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
 313                              TWL4030_BASEADD_GPIO+0x0C);
 314 }
 315 #else
 316 static inline void reset_net_chip(void) {}
 317 #endif
 318
 319 /*
 320  * Routine: handle_mac_address
 321  * Description: prepare MAC address for on-board Ethernet.
 322  */
 323 static int handle_mac_address(void)
 324 {
 325         unsigned char enetaddr[6];
 326         int rc;
 327
 328         rc = eth_getenv_enetaddr("ethaddr", enetaddr);
 329         if (rc)
 330                 return 0;
 331
 332 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
 333         rc = i2c_read(0x50, 0, 1, enetaddr, 6);
 334         if (rc)
 335                 return rc;
 336 #endif
 337
 338         if (!is_valid_ether_addr(enetaddr))
 339                 return -1;
 340
 341         return eth_setenv_enetaddr("ethaddr", enetaddr);
 342 }
 343
 344
 345 /*
 346  * Routine: board_eth_init
 347  * Description: initialize module and base-board Ethernet chips
 348  */
 349 int board_eth_init(bd_t *bis)
 350 {
 351         int rc = 0, rc1 = 0;
 352
 353 #ifdef CONFIG_SMC911X
 354         setup_net_chip_gmpc();
 355         reset_net_chip();
 356
 357         rc1 = handle_mac_address();
 358         if (rc1)
 359                 printf("CM-T35: No MAC address found\n");
 360
 361         rc1 = smc911x_initialize(0, CM_T35_SMC911X_BASE);
 362         if (rc1 > 0)
 363                 rc++;
 364
 365         rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
 366         if (rc1 > 0)
 367                 rc++;
 368 #endif
 369
 370         return rc;
 371 }