2 * Board functions for Compulab CM-FX6 board
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
6 * Author: Nikita Kiryanov <nikita@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <fsl_esdhc.h>
19 #include <fdt_support.h>
22 #include <asm/arch/crm_regs.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/arch/iomux.h>
25 #include <asm/arch/mxc_hdmi.h>
26 #include <asm/mach-imx/mxc_i2c.h>
27 #include <asm/mach-imx/sata.h>
28 #include <asm/mach-imx/video.h>
31 #include <dm/platform_data/serial_mxc.h>
32 #include <jffs2/load_kernel.h>
34 #include "../common/eeprom.h"
35 #include "../common/common.h"
37 DECLARE_GLOBAL_DATA_PTR
;
39 #ifdef CONFIG_SPLASH_SCREEN
40 static struct splash_location cm_fx6_splash_locations
[] = {
43 .storage
= SPLASH_STORAGE_SF
,
44 .flags
= SPLASH_STORAGE_RAW
,
49 .storage
= SPLASH_STORAGE_MMC
,
50 .flags
= SPLASH_STORAGE_FS
,
55 .storage
= SPLASH_STORAGE_USB
,
56 .flags
= SPLASH_STORAGE_FS
,
61 .storage
= SPLASH_STORAGE_SATA
,
62 .flags
= SPLASH_STORAGE_FS
,
67 int splash_screen_prepare(void)
69 return splash_source_load(cm_fx6_splash_locations
,
70 ARRAY_SIZE(cm_fx6_splash_locations
));
74 #ifdef CONFIG_IMX_HDMI
75 static void cm_fx6_enable_hdmi(struct display_info_t
const *dev
)
77 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
79 setbits_le32(&mxc_ccm
->CCGR3
, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK
);
80 imx_enable_hdmi_phy();
83 static struct display_info_t preset_hdmi_1024X768
= {
86 .pixfmt
= IPU_PIX_FMT_RGB24
,
87 .enable
= cm_fx6_enable_hdmi
,
101 .vmode
= FB_VMODE_NONINTERLACED
,
105 static void cm_fx6_setup_display(void)
107 struct iomuxc
*const iomuxc_regs
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
110 clrbits_le32(&iomuxc_regs
->gpr
[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK
);
113 int board_video_skip(void)
116 struct display_info_t
*preset
;
117 char const *panel
= env_get("displaytype");
119 if (!panel
) /* Also accept panel for backward compatibility */
120 panel
= env_get("panel");
125 if (!strcmp(panel
, "HDMI"))
126 preset
= &preset_hdmi_1024X768
;
130 ret
= ipuv3_fb_init(&preset
->mode
, 0, preset
->pixfmt
);
132 printf("Can't init display %s: %d\n", preset
->mode
.name
, ret
);
136 preset
->enable(preset
);
137 printf("Display: %s (%ux%u)\n", preset
->mode
.name
, preset
->mode
.xres
,
143 static inline void cm_fx6_setup_display(void) {}
144 #endif /* CONFIG_VIDEO_IPUV3 */
146 #ifdef CONFIG_DWC_AHSATA
147 static int cm_fx6_issd_gpios
[] = {
148 /* The order of the GPIOs in the array is important! */
153 CM_FX6_SATA_NSTANDBY1
,
154 CM_FX6_SATA_NSTANDBY2
,
157 static void cm_fx6_sata_power(int on
)
161 if (!on
) { /* tell the iSSD that the power will be removed */
162 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT
, 1);
166 for (i
= 0; i
< ARRAY_SIZE(cm_fx6_issd_gpios
); i
++) {
167 gpio_direction_output(cm_fx6_issd_gpios
[i
], on
);
171 if (!on
) /* for compatibility lower the power loss interrupt */
172 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT
, 0);
175 static iomux_v3_cfg_t
const sata_pads
[] = {
177 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
178 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
179 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
180 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
182 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
183 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
184 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
185 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
186 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
189 static int cm_fx6_setup_issd(void)
193 SETUP_IOMUX_PADS(sata_pads
);
195 for (i
= 0; i
< ARRAY_SIZE(cm_fx6_issd_gpios
); i
++) {
196 ret
= gpio_request(cm_fx6_issd_gpios
[i
], "sata");
201 ret
= gpio_request(CM_FX6_SATA_PWLOSS_INT
, "sata_pwloss_int");
208 #define CM_FX6_SATA_INIT_RETRIES 10
209 int sata_initialize(void)
213 /* Make sure this gpio has logical 0 value */
214 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT
, 0);
216 cm_fx6_sata_power(1);
218 for (i
= 0; i
< CM_FX6_SATA_INIT_RETRIES
; i
++) {
221 printf("SATA setup failed: %d\n", err
);
227 err
= __sata_initialize();
231 /* There is no device on the SATA port */
232 if (sata_port_status(0, 0) == 0)
235 /* There's a device, but link not established. Retry */
244 cm_fx6_sata_power(0);
250 static int cm_fx6_setup_issd(void) { return 0; }
253 #ifdef CONFIG_SYS_I2C_MXC
254 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
255 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
256 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
259 PAD_EIM_D21__I2C1_SCL
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
260 PAD_EIM_D21__GPIO3_IO21
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
262 PAD_EIM_D28__I2C1_SDA
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
263 PAD_EIM_D28__GPIO3_IO28
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
267 PAD_KEY_COL3__I2C2_SCL
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
268 PAD_KEY_COL3__GPIO4_IO12
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
270 PAD_KEY_ROW3__I2C2_SDA
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
271 PAD_KEY_ROW3__GPIO4_IO13
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
275 PAD_GPIO_3__I2C3_SCL
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
276 PAD_GPIO_3__GPIO1_IO03
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
278 PAD_GPIO_6__I2C3_SDA
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
279 PAD_GPIO_6__GPIO1_IO06
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
283 static int cm_fx6_setup_one_i2c(int busnum
, struct i2c_pads_info
*pads
)
287 ret
= setup_i2c(busnum
, CONFIG_SYS_I2C_SPEED
, 0x7f, pads
);
289 printf("Warning: I2C%d setup failed: %d\n", busnum
, ret
);
294 static int cm_fx6_setup_i2c(void)
298 /* i2c<x>_pads are wierd macro variables; we can't use an array */
299 err
= cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads
));
302 err
= cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads
));
305 err
= cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads
));
312 static int cm_fx6_setup_i2c(void) { return 0; }
315 #ifdef CONFIG_USB_EHCI_MX6
316 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
317 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
318 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
319 #define MX6_USBNC_BASEADDR 0x2184800
320 #define USBNC_USB_H1_PWR_POL (1 << 9)
322 static int cm_fx6_setup_usb_host(void)
326 err
= gpio_request(CM_FX6_USB_HUB_RST
, "usb hub rst");
330 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR
| MUX_PAD_CTRL(NO_PAD_CTRL
));
331 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08
| MUX_PAD_CTRL(NO_PAD_CTRL
));
336 static int cm_fx6_setup_usb_otg(void)
339 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
341 err
= gpio_request(SB_FX6_USB_OTG_PWR
, "usb-pwr");
343 printf("USB OTG pwr gpio request failed: %d\n", err
);
347 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22
| MUX_PAD_CTRL(NO_PAD_CTRL
));
348 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID
|
349 MUX_PAD_CTRL(WEAK_PULLDOWN
));
350 clrbits_le32(&iomux
->gpr
[1], IOMUXC_GPR1_OTG_ID_MASK
);
351 /* disable ext. charger detect, or it'll affect signal quality at dp. */
352 return gpio_direction_output(SB_FX6_USB_OTG_PWR
, 0);
355 int board_usb_phy_mode(int port
)
357 return USB_INIT_HOST
;
360 int board_ehci_hcd_init(int port
)
363 u32
*usbnc_usb_uh1_ctrl
= (u32
*)(MX6_USBNC_BASEADDR
+ 4);
365 /* Only 1 host controller in use. port 0 is OTG & needs no attention */
369 /* Set PWR polarity to match power switch's enable polarity */
370 setbits_le32(usbnc_usb_uh1_ctrl
, USBNC_USB_H1_PWR_POL
);
371 ret
= gpio_direction_output(CM_FX6_USB_HUB_RST
, 0);
376 ret
= gpio_direction_output(CM_FX6_USB_HUB_RST
, 1);
385 int board_ehci_power(int port
, int on
)
388 return gpio_direction_output(SB_FX6_USB_OTG_PWR
, on
);
393 static int cm_fx6_setup_usb_otg(void) { return 0; }
394 static int cm_fx6_setup_usb_host(void) { return 0; }
397 #ifdef CONFIG_FEC_MXC
398 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
399 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
401 static int mx6_rgmii_rework(struct phy_device
*phydev
)
405 /* Ar8031 phy SmartEEE feature cause link status generates glitch,
406 * which cause ethernet link down/up issue, so disable SmartEEE
408 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xd, 0x3);
409 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xe, 0x805d);
410 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xd, 0x4003);
411 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, 0xe);
413 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xe, val
);
415 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
416 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xd, 0x7);
417 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xe, 0x8016);
418 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xd, 0x4007);
420 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, 0xe);
423 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xe, val
);
425 /* introduce tx clock delay */
426 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1d, 0x5);
427 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, 0x1e);
429 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, val
);
434 int board_phy_config(struct phy_device
*phydev
)
436 mx6_rgmii_rework(phydev
);
438 if (phydev
->drv
->config
)
439 return phydev
->drv
->config(phydev
);
444 static iomux_v3_cfg_t
const enet_pads
[] = {
445 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
446 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
447 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
448 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
449 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
450 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
451 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
452 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
453 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
454 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
455 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
456 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
457 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
458 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
459 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08
| MUX_PAD_CTRL(0x84)),
460 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
|
461 MUX_PAD_CTRL(ENET_PAD_CTRL
)),
462 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
|
463 MUX_PAD_CTRL(ENET_PAD_CTRL
)),
464 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
|
465 MUX_PAD_CTRL(ENET_PAD_CTRL
)),
468 static int handle_mac_address(char *env_var
, uint eeprom_bus
)
470 unsigned char enetaddr
[6];
473 rc
= eth_getenv_enetaddr(env_var
, enetaddr
);
477 rc
= cl_eeprom_read_mac_addr(enetaddr
, eeprom_bus
);
481 if (!is_valid_ethaddr(enetaddr
))
484 return eth_env_set_enetaddr(env_var
, enetaddr
);
487 #define SB_FX6_I2C_EEPROM_BUS 0
488 #define NO_MAC_ADDR "No MAC address found for %s\n"
489 int board_eth_init(bd_t
*bis
)
493 if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS
))
494 printf(NO_MAC_ADDR
, "primary NIC");
496 if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS
))
497 printf(NO_MAC_ADDR
, "secondary NIC");
499 SETUP_IOMUX_PADS(enet_pads
);
501 err
= gpio_request(CM_FX6_ENET_NRST
, "enet_nrst");
503 printf("Etnernet NRST gpio request failed: %d\n", err
);
504 gpio_direction_output(CM_FX6_ENET_NRST
, 0);
506 gpio_set_value(CM_FX6_ENET_NRST
, 1);
508 return cpu_eth_init(bis
);
512 #ifdef CONFIG_NAND_MXS
513 static iomux_v3_cfg_t
const nand_pads
[] = {
514 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
515 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
516 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
517 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
518 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
519 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
520 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
521 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
522 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
523 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
524 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
525 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
526 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
527 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
530 static void cm_fx6_setup_gpmi_nand(void)
532 SETUP_IOMUX_PADS(nand_pads
);
533 /* Enable clock roots */
534 enable_usdhc_clk(1, 3);
535 enable_usdhc_clk(1, 4);
537 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
538 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
539 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
542 static void cm_fx6_setup_gpmi_nand(void) {}
545 #ifdef CONFIG_FSL_ESDHC
546 static struct fsl_esdhc_cfg usdhc_cfg
[3] = {
552 static enum mxc_clock usdhc_clk
[3] = {
558 int board_mmc_init(bd_t
*bis
)
562 cm_fx6_set_usdhc_iomux();
563 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
564 usdhc_cfg
[i
].sdhc_clk
= mxc_get_clock(usdhc_clk
[i
]);
565 usdhc_cfg
[i
].max_bus_width
= 4;
566 fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
567 enable_usdhc_clk(1, i
);
574 #ifdef CONFIG_MXC_SPI
575 int cm_fx6_setup_ecspi(void)
577 cm_fx6_set_ecspi_iomux();
578 return gpio_request(CM_FX6_ECSPI_BUS0_CS0
, "ecspi_bus0_cs0");
581 int cm_fx6_setup_ecspi(void) { return 0; }
584 #ifdef CONFIG_OF_BOARD_SETUP
585 #define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/"
587 struct node_info nodes
[] = {
589 * Both entries target the same flash chip. The st,m25p compatible
590 * is used in the vendor device trees, while upstream uses (the
591 * documented) jedec,spi-nor compatible.
593 { "st,m25p", MTD_DEV_TYPE_NOR
, },
594 { "jedec,spi-nor", MTD_DEV_TYPE_NOR
, },
597 int ft_board_setup(void *blob
, bd_t
*bd
)
602 char baseboard_name
[16];
605 fdt_shrink_to_minimum(blob
, 0); /* Make room for new properties */
608 if (eth_getenv_enetaddr("ethaddr", enetaddr
)) {
609 fdt_find_and_setprop(blob
,
610 "/soc/aips-bus@02100000/ethernet@02188000",
611 "local-mac-address", enetaddr
, 6, 1);
614 if (eth_getenv_enetaddr("eth1addr", enetaddr
)) {
615 fdt_find_and_setprop(blob
, "/eth@pcie", "local-mac-address",
619 fdt_fixup_mtdparts(blob
, nodes
, ARRAY_SIZE(nodes
));
621 baseboard_rev
= cl_eeprom_get_board_rev(0);
622 err
= cl_eeprom_get_product_name((uchar
*)baseboard_name
, 0);
623 if (err
|| baseboard_rev
== 0)
624 return 0; /* Assume not an early revision SB-FX6m baseboard */
626 if (!strncmp("SB-FX6m", baseboard_name
, 7) && baseboard_rev
<= 120) {
627 nodeoffset
= fdt_path_offset(blob
, USDHC3_PATH
);
628 fdt_delprop(blob
, nodeoffset
, "cd-gpios");
629 fdt_find_and_setprop(blob
, USDHC3_PATH
, "broken-cd",
631 fdt_find_and_setprop(blob
, USDHC3_PATH
, "keep-power-in-suspend",
643 gd
->bd
->bi_boot_params
= PHYS_SDRAM_1
+ 0x100;
644 cm_fx6_setup_gpmi_nand();
646 ret
= cm_fx6_setup_ecspi();
648 printf("Warning: ECSPI setup failed: %d\n", ret
);
650 ret
= cm_fx6_setup_usb_otg();
652 printf("Warning: USB OTG setup failed: %d\n", ret
);
654 ret
= cm_fx6_setup_usb_host();
656 printf("Warning: USB host setup failed: %d\n", ret
);
659 * cm-fx6 may have iSSD not assembled and in this case it has
660 * bypasses for a (m)SATA socket on the baseboard. The socketed
661 * device is not controlled by those GPIOs. So just print a warning
662 * if the setup fails.
664 ret
= cm_fx6_setup_issd();
666 printf("Warning: iSSD setup failed: %d\n", ret
);
668 /* Warn on failure but do not abort boot */
669 ret
= cm_fx6_setup_i2c();
671 printf("Warning: I2C setup failed: %d\n", ret
);
673 cm_fx6_setup_display();
680 puts("Board: CM-FX6\n");
684 int misc_init_r(void)
691 int dram_init_banksize(void)
693 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM_1
;
694 gd
->bd
->bi_dram
[1].start
= PHYS_SDRAM_2
;
696 switch (gd
->ram_size
) {
697 case 0x10000000: /* DDR_16BIT_256MB */
698 gd
->bd
->bi_dram
[0].size
= 0x10000000;
699 gd
->bd
->bi_dram
[1].size
= 0;
701 case 0x20000000: /* DDR_32BIT_512MB */
702 gd
->bd
->bi_dram
[0].size
= 0x20000000;
703 gd
->bd
->bi_dram
[1].size
= 0;
706 if (is_cpu_type(MXC_CPU_MX6SOLO
)) { /* DDR_32BIT_1GB */
707 gd
->bd
->bi_dram
[0].size
= 0x20000000;
708 gd
->bd
->bi_dram
[1].size
= 0x20000000;
709 } else { /* DDR_64BIT_1GB */
710 gd
->bd
->bi_dram
[0].size
= 0x40000000;
711 gd
->bd
->bi_dram
[1].size
= 0;
714 case 0x80000000: /* DDR_64BIT_2GB */
715 gd
->bd
->bi_dram
[0].size
= 0x40000000;
716 gd
->bd
->bi_dram
[1].size
= 0x40000000;
718 case 0xEFF00000: /* DDR_64BIT_4GB */
719 gd
->bd
->bi_dram
[0].size
= 0x70000000;
720 gd
->bd
->bi_dram
[1].size
= 0x7FF00000;
729 gd
->ram_size
= imx_ddr_size();
730 switch (gd
->ram_size
) {
737 gd
->ram_size
-= 0x100000;
740 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd
->ram_size
);
747 u32
get_board_rev(void)
749 return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS
);
752 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat
= {
753 .reg
= (struct mxc_uart
*)UART4_BASE
,
756 U_BOOT_DEVICE(cm_fx6_serial
) = {
757 .name
= "serial_mxc",
758 .platdata
= &cm_fx6_mxc_serial_plat
,