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arm: mx6: cm-fx6: add hdmi console support
[people/ms/u-boot.git] / board / compulab / cm_fx6 / cm_fx6.c
1 /*
2 * Board functions for Compulab CM-FX6 board
3 *
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
5 *
6 * Author: Nikita Kiryanov <nikita@compulab.co.il>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <common.h>
12 #include <dm.h>
13 #include <fsl_esdhc.h>
14 #include <miiphy.h>
15 #include <netdev.h>
16 #include <fdt_support.h>
17 #include <sata.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/arch/iomux.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/imx-common/mxc_i2c.h>
23 #include <asm/imx-common/sata.h>
24 #include <asm/imx-common/video.h>
25 #include <asm/io.h>
26 #include <asm/gpio.h>
27 #include <dm/platform_data/serial_mxc.h>
28 #include "common.h"
29 #include "../common/eeprom.h"
30
31 DECLARE_GLOBAL_DATA_PTR;
32
33 #ifdef CONFIG_IMX_HDMI
34 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
35 {
36 imx_enable_hdmi_phy();
37 }
38
39 struct display_info_t const displays[] = {
40 {
41 .bus = -1,
42 .addr = 0,
43 .pixfmt = IPU_PIX_FMT_RGB24,
44 .detect = detect_hdmi,
45 .enable = cm_fx6_enable_hdmi,
46 .mode = {
47 .name = "HDMI",
48 .refresh = 60,
49 .xres = 1024,
50 .yres = 768,
51 .pixclock = 40385,
52 .left_margin = 220,
53 .right_margin = 40,
54 .upper_margin = 21,
55 .lower_margin = 7,
56 .hsync_len = 60,
57 .vsync_len = 10,
58 .sync = FB_SYNC_EXT,
59 .vmode = FB_VMODE_NONINTERLACED,
60 }
61 },
62 };
63 size_t display_count = ARRAY_SIZE(displays);
64
65 static void cm_fx6_setup_display(void)
66 {
67 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
68 int reg;
69
70 enable_ipu_clock();
71 imx_setup_hdmi();
72 reg = __raw_readl(&mxc_ccm->CCGR3);
73 reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK;
74 writel(reg, &mxc_ccm->CCGR3);
75 }
76 #else
77 static inline void cm_fx6_setup_display(void) {}
78 #endif /* CONFIG_VIDEO_IPUV3 */
79
80 #ifdef CONFIG_DWC_AHSATA
81 static int cm_fx6_issd_gpios[] = {
82 /* The order of the GPIOs in the array is important! */
83 CM_FX6_SATA_LDO_EN,
84 CM_FX6_SATA_PHY_SLP,
85 CM_FX6_SATA_NRSTDLY,
86 CM_FX6_SATA_PWREN,
87 CM_FX6_SATA_NSTANDBY1,
88 CM_FX6_SATA_NSTANDBY2,
89 };
90
91 static void cm_fx6_sata_power(int on)
92 {
93 int i;
94
95 if (!on) { /* tell the iSSD that the power will be removed */
96 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
97 mdelay(10);
98 }
99
100 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
101 gpio_direction_output(cm_fx6_issd_gpios[i], on);
102 udelay(100);
103 }
104
105 if (!on) /* for compatibility lower the power loss interrupt */
106 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
107 }
108
109 static iomux_v3_cfg_t const sata_pads[] = {
110 /* SATA PWR */
111 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
112 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
113 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
114 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
115 /* SATA CTRL */
116 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
117 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
118 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
119 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
120 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
121 };
122
123 static int cm_fx6_setup_issd(void)
124 {
125 int ret, i;
126
127 SETUP_IOMUX_PADS(sata_pads);
128
129 for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
130 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
131 if (ret)
132 return ret;
133 }
134
135 ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
136 if (ret)
137 return ret;
138
139 return 0;
140 }
141
142 #define CM_FX6_SATA_INIT_RETRIES 10
143 int sata_initialize(void)
144 {
145 int err, i;
146
147 /* Make sure this gpio has logical 0 value */
148 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
149 udelay(100);
150 cm_fx6_sata_power(1);
151
152 for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
153 err = setup_sata();
154 if (err) {
155 printf("SATA setup failed: %d\n", err);
156 return err;
157 }
158
159 udelay(100);
160
161 err = __sata_initialize();
162 if (!err)
163 break;
164
165 /* There is no device on the SATA port */
166 if (sata_port_status(0, 0) == 0)
167 break;
168
169 /* There's a device, but link not established. Retry */
170 }
171
172 return err;
173 }
174
175 int sata_stop(void)
176 {
177 __sata_stop();
178 cm_fx6_sata_power(0);
179 mdelay(250);
180
181 return 0;
182 }
183 #else
184 static int cm_fx6_setup_issd(void) { return 0; }
185 #endif
186
187 #ifdef CONFIG_SYS_I2C_MXC
188 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
189 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
190 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
191
192 I2C_PADS(i2c0_pads,
193 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
194 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
195 IMX_GPIO_NR(3, 21),
196 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
197 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
198 IMX_GPIO_NR(3, 28));
199
200 I2C_PADS(i2c1_pads,
201 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
202 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
203 IMX_GPIO_NR(4, 12),
204 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
205 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
206 IMX_GPIO_NR(4, 13));
207
208 I2C_PADS(i2c2_pads,
209 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
210 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
211 IMX_GPIO_NR(1, 3),
212 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
213 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
214 IMX_GPIO_NR(1, 6));
215
216
217 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
218 {
219 int ret;
220
221 ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
222 if (ret)
223 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
224
225 return ret;
226 }
227
228 static int cm_fx6_setup_i2c(void)
229 {
230 int ret = 0, err;
231
232 /* i2c<x>_pads are wierd macro variables; we can't use an array */
233 err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
234 if (err)
235 ret = err;
236 err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
237 if (err)
238 ret = err;
239 err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
240 if (err)
241 ret = err;
242
243 return ret;
244 }
245 #else
246 static int cm_fx6_setup_i2c(void) { return 0; }
247 #endif
248
249 #ifdef CONFIG_USB_EHCI_MX6
250 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
251 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
252 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
253 #define MX6_USBNC_BASEADDR 0x2184800
254 #define USBNC_USB_H1_PWR_POL (1 << 9)
255
256 static int cm_fx6_setup_usb_host(void)
257 {
258 int err;
259
260 err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
261 if (err)
262 return err;
263
264 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
265 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
266
267 return 0;
268 }
269
270 static int cm_fx6_setup_usb_otg(void)
271 {
272 int err;
273 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
274
275 err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
276 if (err) {
277 printf("USB OTG pwr gpio request failed: %d\n", err);
278 return err;
279 }
280
281 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
282 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
283 MUX_PAD_CTRL(WEAK_PULLDOWN));
284 clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
285 /* disable ext. charger detect, or it'll affect signal quality at dp. */
286 return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
287 }
288
289 int board_ehci_hcd_init(int port)
290 {
291 int ret;
292 u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
293
294 /* Only 1 host controller in use. port 0 is OTG & needs no attention */
295 if (port != 1)
296 return 0;
297
298 /* Set PWR polarity to match power switch's enable polarity */
299 setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
300 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
301 if (ret)
302 return ret;
303
304 udelay(10);
305 ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
306 if (ret)
307 return ret;
308
309 mdelay(1);
310
311 return 0;
312 }
313
314 int board_ehci_power(int port, int on)
315 {
316 if (port == 0)
317 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
318
319 return 0;
320 }
321 #else
322 static int cm_fx6_setup_usb_otg(void) { return 0; }
323 static int cm_fx6_setup_usb_host(void) { return 0; }
324 #endif
325
326 #ifdef CONFIG_FEC_MXC
327 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
328 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
329
330 static int mx6_rgmii_rework(struct phy_device *phydev)
331 {
332 unsigned short val;
333
334 /* Ar8031 phy SmartEEE feature cause link status generates glitch,
335 * which cause ethernet link down/up issue, so disable SmartEEE
336 */
337 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
338 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
339 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
340 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
341 val &= ~(0x1 << 8);
342 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
343
344 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
345 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
346 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
347 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
348
349 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
350 val &= 0xffe3;
351 val |= 0x18;
352 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
353
354 /* introduce tx clock delay */
355 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
356 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
357 val |= 0x0100;
358 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
359
360 return 0;
361 }
362
363 int board_phy_config(struct phy_device *phydev)
364 {
365 mx6_rgmii_rework(phydev);
366
367 if (phydev->drv->config)
368 return phydev->drv->config(phydev);
369
370 return 0;
371 }
372
373 static iomux_v3_cfg_t const enet_pads[] = {
374 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
375 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
376 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
377 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
378 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
379 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
380 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
381 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
382 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
383 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
384 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
385 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
386 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
387 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
388 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
389 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
390 MUX_PAD_CTRL(ENET_PAD_CTRL)),
391 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
392 MUX_PAD_CTRL(ENET_PAD_CTRL)),
393 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
394 MUX_PAD_CTRL(ENET_PAD_CTRL)),
395 };
396
397 static int handle_mac_address(char *env_var, uint eeprom_bus)
398 {
399 unsigned char enetaddr[6];
400 int rc;
401
402 rc = eth_getenv_enetaddr(env_var, enetaddr);
403 if (rc)
404 return 0;
405
406 rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
407 if (rc)
408 return rc;
409
410 if (!is_valid_ether_addr(enetaddr))
411 return -1;
412
413 return eth_setenv_enetaddr(env_var, enetaddr);
414 }
415
416 #define SB_FX6_I2C_EEPROM_BUS 0
417 #define NO_MAC_ADDR "No MAC address found for %s\n"
418 int board_eth_init(bd_t *bis)
419 {
420 int err;
421
422 if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
423 printf(NO_MAC_ADDR, "primary NIC");
424
425 if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
426 printf(NO_MAC_ADDR, "secondary NIC");
427
428 SETUP_IOMUX_PADS(enet_pads);
429 /* phy reset */
430 err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
431 if (err)
432 printf("Etnernet NRST gpio request failed: %d\n", err);
433 gpio_direction_output(CM_FX6_ENET_NRST, 0);
434 udelay(500);
435 gpio_set_value(CM_FX6_ENET_NRST, 1);
436 enable_enet_clk(1);
437 return cpu_eth_init(bis);
438 }
439 #endif
440
441 #ifdef CONFIG_NAND_MXS
442 static iomux_v3_cfg_t const nand_pads[] = {
443 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
444 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
445 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
446 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
447 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
448 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
449 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
450 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
451 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
452 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
453 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
454 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
455 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
456 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
457 };
458
459 static void cm_fx6_setup_gpmi_nand(void)
460 {
461 SETUP_IOMUX_PADS(nand_pads);
462 /* Enable clock roots */
463 enable_usdhc_clk(1, 3);
464 enable_usdhc_clk(1, 4);
465
466 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
467 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
468 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
469 }
470 #else
471 static void cm_fx6_setup_gpmi_nand(void) {}
472 #endif
473
474 #ifdef CONFIG_FSL_ESDHC
475 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
476 {USDHC1_BASE_ADDR},
477 {USDHC2_BASE_ADDR},
478 {USDHC3_BASE_ADDR},
479 };
480
481 static enum mxc_clock usdhc_clk[3] = {
482 MXC_ESDHC_CLK,
483 MXC_ESDHC2_CLK,
484 MXC_ESDHC3_CLK,
485 };
486
487 int board_mmc_init(bd_t *bis)
488 {
489 int i;
490
491 cm_fx6_set_usdhc_iomux();
492 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
493 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
494 usdhc_cfg[i].max_bus_width = 4;
495 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
496 enable_usdhc_clk(1, i);
497 }
498
499 return 0;
500 }
501 #endif
502
503 #ifdef CONFIG_MXC_SPI
504 int cm_fx6_setup_ecspi(void)
505 {
506 cm_fx6_set_ecspi_iomux();
507 return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
508 }
509 #else
510 int cm_fx6_setup_ecspi(void) { return 0; }
511 #endif
512
513 #ifdef CONFIG_OF_BOARD_SETUP
514 int ft_board_setup(void *blob, bd_t *bd)
515 {
516 uint8_t enetaddr[6];
517
518 /* MAC addr */
519 if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
520 fdt_find_and_setprop(blob,
521 "/soc/aips-bus@02100000/ethernet@02188000",
522 "local-mac-address", enetaddr, 6, 1);
523 }
524
525 if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
526 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
527 enetaddr, 6, 1);
528 }
529
530 return 0;
531 }
532 #endif
533
534 int board_init(void)
535 {
536 int ret;
537
538 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
539 cm_fx6_setup_gpmi_nand();
540
541 ret = cm_fx6_setup_ecspi();
542 if (ret)
543 printf("Warning: ECSPI setup failed: %d\n", ret);
544
545 ret = cm_fx6_setup_usb_otg();
546 if (ret)
547 printf("Warning: USB OTG setup failed: %d\n", ret);
548
549 ret = cm_fx6_setup_usb_host();
550 if (ret)
551 printf("Warning: USB host setup failed: %d\n", ret);
552
553 /*
554 * cm-fx6 may have iSSD not assembled and in this case it has
555 * bypasses for a (m)SATA socket on the baseboard. The socketed
556 * device is not controlled by those GPIOs. So just print a warning
557 * if the setup fails.
558 */
559 ret = cm_fx6_setup_issd();
560 if (ret)
561 printf("Warning: iSSD setup failed: %d\n", ret);
562
563 /* Warn on failure but do not abort boot */
564 ret = cm_fx6_setup_i2c();
565 if (ret)
566 printf("Warning: I2C setup failed: %d\n", ret);
567
568 cm_fx6_setup_display();
569
570 return 0;
571 }
572
573 int checkboard(void)
574 {
575 puts("Board: CM-FX6\n");
576 return 0;
577 }
578
579 void dram_init_banksize(void)
580 {
581 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
582 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
583
584 switch (gd->ram_size) {
585 case 0x10000000: /* DDR_16BIT_256MB */
586 gd->bd->bi_dram[0].size = 0x10000000;
587 gd->bd->bi_dram[1].size = 0;
588 break;
589 case 0x20000000: /* DDR_32BIT_512MB */
590 gd->bd->bi_dram[0].size = 0x20000000;
591 gd->bd->bi_dram[1].size = 0;
592 break;
593 case 0x40000000:
594 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
595 gd->bd->bi_dram[0].size = 0x20000000;
596 gd->bd->bi_dram[1].size = 0x20000000;
597 } else { /* DDR_64BIT_1GB */
598 gd->bd->bi_dram[0].size = 0x40000000;
599 gd->bd->bi_dram[1].size = 0;
600 }
601 break;
602 case 0x80000000: /* DDR_64BIT_2GB */
603 gd->bd->bi_dram[0].size = 0x40000000;
604 gd->bd->bi_dram[1].size = 0x40000000;
605 break;
606 case 0xEFF00000: /* DDR_64BIT_4GB */
607 gd->bd->bi_dram[0].size = 0x70000000;
608 gd->bd->bi_dram[1].size = 0x7FF00000;
609 break;
610 }
611 }
612
613 int dram_init(void)
614 {
615 gd->ram_size = imx_ddr_size();
616 switch (gd->ram_size) {
617 case 0x10000000:
618 case 0x20000000:
619 case 0x40000000:
620 case 0x80000000:
621 break;
622 case 0xF0000000:
623 gd->ram_size -= 0x100000;
624 break;
625 default:
626 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
627 return -1;
628 }
629
630 return 0;
631 }
632
633 u32 get_board_rev(void)
634 {
635 return cl_eeprom_get_board_rev();
636 }
637
638 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
639 .reg = (struct mxc_uart *)UART4_BASE,
640 };
641
642 U_BOOT_DEVICE(cm_fx6_serial) = {
643 .name = "serial_mxc",
644 .platdata = &cm_fx6_mxc_serial_plat,
645 };
"Das U-Boot" Source Tree