board/compulab/cm_fx6/cm_fx6.c

   1 /*
   2  * Board functions for Compulab CM-FX6 board
   3  *
   4  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <ahci.h>
  13 #include <dm.h>
  14 #include <dwc_ahsata.h>
  15 #include <fsl_esdhc.h>
  16 #include <miiphy.h>
  17 #include <mtd_node.h>
  18 #include <netdev.h>
  19 #include <errno.h>
  20 #include <usb.h>
  21 #include <fdt_support.h>
  22 #include <sata.h>
  23 #include <splash.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/arch/iomux.h>
  27 #include <asm/arch/mxc_hdmi.h>
  28 #include <asm/mach-imx/mxc_i2c.h>
  29 #include <asm/mach-imx/sata.h>
  30 #include <asm/mach-imx/video.h>
  31 #include <asm/io.h>
  32 #include <asm/gpio.h>
  33 #include <dm/platform_data/serial_mxc.h>
  34 #include <dm/device-internal.h>
  35 #include <jffs2/load_kernel.h>
  36 #include "common.h"
  37 #include "../common/eeprom.h"
  38 #include "../common/common.h"
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 #ifdef CONFIG_SPLASH_SCREEN
  43 static struct splash_location cm_fx6_splash_locations[] = {
  44         {
  45                 .name = "sf",
  46                 .storage = SPLASH_STORAGE_SF,
  47                 .flags = SPLASH_STORAGE_RAW,
  48                 .offset = 0x100000,
  49         },
  50         {
  51                 .name = "mmc_fs",
  52                 .storage = SPLASH_STORAGE_MMC,
  53                 .flags = SPLASH_STORAGE_FS,
  54                 .devpart = "2:1",
  55         },
  56         {
  57                 .name = "usb_fs",
  58                 .storage = SPLASH_STORAGE_USB,
  59                 .flags = SPLASH_STORAGE_FS,
  60                 .devpart = "0:1",
  61         },
  62         {
  63                 .name = "sata_fs",
  64                 .storage = SPLASH_STORAGE_SATA,
  65                 .flags = SPLASH_STORAGE_FS,
  66                 .devpart = "0:1",
  67         },
  68 };
  69
  70 int splash_screen_prepare(void)
  71 {
  72         return splash_source_load(cm_fx6_splash_locations,
  73                                   ARRAY_SIZE(cm_fx6_splash_locations));
  74 }
  75 #endif
  76
  77 #ifdef CONFIG_IMX_HDMI
  78 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
  79 {
  80         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  81         imx_setup_hdmi();
  82         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
  83         imx_enable_hdmi_phy();
  84 }
  85
  86 static struct display_info_t preset_hdmi_1024X768 = {
  87         .bus    = -1,
  88         .addr   = 0,
  89         .pixfmt = IPU_PIX_FMT_RGB24,
  90         .enable = cm_fx6_enable_hdmi,
  91         .mode   = {
  92                 .name           = "HDMI",
  93                 .refresh        = 60,
  94                 .xres           = 1024,
  95                 .yres           = 768,
  96                 .pixclock       = 40385,
  97                 .left_margin    = 220,
  98                 .right_margin   = 40,
  99                 .upper_margin   = 21,
 100                 .lower_margin   = 7,
 101                 .hsync_len      = 60,
 102                 .vsync_len      = 10,
 103                 .sync           = FB_SYNC_EXT,
 104                 .vmode          = FB_VMODE_NONINTERLACED,
 105         }
 106 };
 107
 108 static void cm_fx6_setup_display(void)
 109 {
 110         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 111
 112         enable_ipu_clock();
 113         clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
 114 }
 115
 116 int board_video_skip(void)
 117 {
 118         int ret;
 119         struct display_info_t *preset;
 120         char const *panel = getenv("displaytype");
 121
 122         if (!panel) /* Also accept panel for backward compatibility */
 123                 panel = getenv("panel");
 124
 125         if (!panel)
 126                 return -ENOENT;
 127
 128         if (!strcmp(panel, "HDMI"))
 129                 preset = &preset_hdmi_1024X768;
 130         else
 131                 return -EINVAL;
 132
 133         ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
 134         if (ret) {
 135                 printf("Can't init display %s: %d\n", preset->mode.name, ret);
 136                 return ret;
 137         }
 138
 139         preset->enable(preset);
 140         printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
 141                preset->mode.yres);
 142
 143         return 0;
 144 }
 145 #else
 146 static inline void cm_fx6_setup_display(void) {}
 147 #endif /* CONFIG_VIDEO_IPUV3 */
 148
 149 #ifdef CONFIG_DWC_AHSATA
 150 static int cm_fx6_issd_gpios[] = {
 151         /* The order of the GPIOs in the array is important! */
 152         CM_FX6_SATA_LDO_EN,
 153         CM_FX6_SATA_PHY_SLP,
 154         CM_FX6_SATA_NRSTDLY,
 155         CM_FX6_SATA_PWREN,
 156         CM_FX6_SATA_NSTANDBY1,
 157         CM_FX6_SATA_NSTANDBY2,
 158 };
 159
 160 static void cm_fx6_sata_power(int on)
 161 {
 162         int i;
 163
 164         if (!on) { /* tell the iSSD that the power will be removed */
 165                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
 166                 mdelay(10);
 167         }
 168
 169         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 170                 gpio_direction_output(cm_fx6_issd_gpios[i], on);
 171                 udelay(100);
 172         }
 173
 174         if (!on) /* for compatibility lower the power loss interrupt */
 175                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 176 }
 177
 178 static iomux_v3_cfg_t const sata_pads[] = {
 179         /* SATA PWR */
 180         IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 181         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 182         IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 183         IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 184         /* SATA CTRL */
 185         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 186         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 187         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 188         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 189         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 190 };
 191
 192 static int cm_fx6_setup_issd(void)
 193 {
 194         int ret, i;
 195
 196         SETUP_IOMUX_PADS(sata_pads);
 197
 198         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 199                 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
 200                 if (ret)
 201                         return ret;
 202         }
 203
 204         ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
 205         if (ret)
 206                 return ret;
 207
 208         return 0;
 209 }
 210
 211 #define CM_FX6_SATA_INIT_RETRIES        10
 212
 213 # if !CONFIG_IS_ENABLED(AHCI)
 214 int sata_initialize(void)
 215 {
 216         int err, i;
 217
 218         /* Make sure this gpio has logical 0 value */
 219         gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 220         udelay(100);
 221         cm_fx6_sata_power(1);
 222
 223         for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
 224                 err = setup_sata();
 225                 if (err) {
 226                         printf("SATA setup failed: %d\n", err);
 227                         return err;
 228                 }
 229
 230                 udelay(100);
 231
 232                 err = __sata_initialize();
 233                 if (!err)
 234                         break;
 235
 236                 /* There is no device on the SATA port */
 237                 if (sata_port_status(0, 0) == 0)
 238                         break;
 239
 240                 /* There's a device, but link not established. Retry */
 241         }
 242
 243         return err;
 244 }
 245
 246 int sata_stop(void)
 247 {
 248         __sata_stop();
 249         cm_fx6_sata_power(0);
 250         mdelay(250);
 251
 252         return 0;
 253 }
 254 # endif
 255 #else
 256 static int cm_fx6_setup_issd(void) { return 0; }
 257 #endif
 258
 259 #ifdef CONFIG_SYS_I2C_MXC
 260 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 261                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
 262                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 263
 264 I2C_PADS(i2c0_pads,
 265          PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 266          PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 267          IMX_GPIO_NR(3, 21),
 268          PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 269          PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 270          IMX_GPIO_NR(3, 28));
 271
 272 I2C_PADS(i2c1_pads,
 273          PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 274          PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 275          IMX_GPIO_NR(4, 12),
 276          PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 277          PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 278          IMX_GPIO_NR(4, 13));
 279
 280 I2C_PADS(i2c2_pads,
 281          PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 282          PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 283          IMX_GPIO_NR(1, 3),
 284          PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 285          PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 286          IMX_GPIO_NR(1, 6));
 287
 288
 289 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
 290 {
 291         int ret;
 292
 293         ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
 294         if (ret)
 295                 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
 296
 297         return ret;
 298 }
 299
 300 static int cm_fx6_setup_i2c(void)
 301 {
 302         int ret = 0, err;
 303
 304         /* i2c<x>_pads are wierd macro variables; we can't use an array */
 305         err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
 306         if (err)
 307                 ret = err;
 308         err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
 309         if (err)
 310                 ret = err;
 311         err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
 312         if (err)
 313                 ret = err;
 314
 315         return ret;
 316 }
 317 #else
 318 static int cm_fx6_setup_i2c(void) { return 0; }
 319 #endif
 320
 321 #ifdef CONFIG_USB_EHCI_MX6
 322 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
 323                         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 324                         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 325 #define MX6_USBNC_BASEADDR      0x2184800
 326 #define USBNC_USB_H1_PWR_POL    (1 << 9)
 327
 328 static int cm_fx6_setup_usb_host(void)
 329 {
 330         int err;
 331
 332         err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
 333         if (err)
 334                 return err;
 335
 336         SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
 337         SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
 338
 339         return 0;
 340 }
 341
 342 static int cm_fx6_setup_usb_otg(void)
 343 {
 344         int err;
 345         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 346
 347         err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
 348         if (err) {
 349                 printf("USB OTG pwr gpio request failed: %d\n", err);
 350                 return err;
 351         }
 352
 353         SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
 354         SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
 355                                                 MUX_PAD_CTRL(WEAK_PULLDOWN));
 356         clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
 357         /* disable ext. charger detect, or it'll affect signal quality at dp. */
 358         return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 359 }
 360
 361 int board_usb_phy_mode(int port)
 362 {
 363         return USB_INIT_HOST;
 364 }
 365
 366 int board_ehci_hcd_init(int port)
 367 {
 368         int ret;
 369         u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 370
 371         /* Only 1 host controller in use. port 0 is OTG & needs no attention */
 372         if (port != 1)
 373                 return 0;
 374
 375         /* Set PWR polarity to match power switch's enable polarity */
 376         setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
 377         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
 378         if (ret)
 379                 return ret;
 380
 381         udelay(10);
 382         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
 383         if (ret)
 384                 return ret;
 385
 386         mdelay(1);
 387
 388         return 0;
 389 }
 390
 391 int board_ehci_power(int port, int on)
 392 {
 393         if (port == 0)
 394                 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
 395
 396         return 0;
 397 }
 398 #else
 399 static int cm_fx6_setup_usb_otg(void) { return 0; }
 400 static int cm_fx6_setup_usb_host(void) { return 0; }
 401 #endif
 402
 403 #ifdef CONFIG_FEC_MXC
 404 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 405                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 406
 407 static int mx6_rgmii_rework(struct phy_device *phydev)
 408 {
 409         unsigned short val;
 410
 411         /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 412          * which cause ethernet link down/up issue, so disable SmartEEE
 413          */
 414         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 415         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 416         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 417         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 418         val &= ~(0x1 << 8);
 419         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 420
 421         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 422         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 423         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 424         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 425
 426         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 427         val &= 0xffe3;
 428         val |= 0x18;
 429         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 430
 431         /* introduce tx clock delay */
 432         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 433         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 434         val |= 0x0100;
 435         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 436
 437         return 0;
 438 }
 439
 440 int board_phy_config(struct phy_device *phydev)
 441 {
 442         mx6_rgmii_rework(phydev);
 443
 444         if (phydev->drv->config)
 445                 return phydev->drv->config(phydev);
 446
 447         return 0;
 448 }
 449
 450 static iomux_v3_cfg_t const enet_pads[] = {
 451         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 452         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 453         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 454         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 455         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 456         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 457         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 458         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 459         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 460         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 461         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 462         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 463         IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 464         IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 465         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
 466         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
 467                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 468         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 469                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 470         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 471                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 472 };
 473
 474 static int handle_mac_address(char *env_var, uint eeprom_bus)
 475 {
 476         unsigned char enetaddr[6];
 477         int rc;
 478
 479         rc = eth_getenv_enetaddr(env_var, enetaddr);
 480         if (rc)
 481                 return 0;
 482
 483         rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
 484         if (rc)
 485                 return rc;
 486
 487         if (!is_valid_ethaddr(enetaddr))
 488                 return -1;
 489
 490         return eth_setenv_enetaddr(env_var, enetaddr);
 491 }
 492
 493 #define SB_FX6_I2C_EEPROM_BUS   0
 494 #define NO_MAC_ADDR             "No MAC address found for %s\n"
 495 int board_eth_init(bd_t *bis)
 496 {
 497         int err;
 498
 499         if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
 500                 printf(NO_MAC_ADDR, "primary NIC");
 501
 502         if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
 503                 printf(NO_MAC_ADDR, "secondary NIC");
 504
 505         SETUP_IOMUX_PADS(enet_pads);
 506         /* phy reset */
 507         err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
 508         if (err)
 509                 printf("Etnernet NRST gpio request failed: %d\n", err);
 510         gpio_direction_output(CM_FX6_ENET_NRST, 0);
 511         udelay(500);
 512         gpio_set_value(CM_FX6_ENET_NRST, 1);
 513         enable_enet_clk(1);
 514         return cpu_eth_init(bis);
 515 }
 516 #endif
 517
 518 #ifdef CONFIG_NAND_MXS
 519 static iomux_v3_cfg_t const nand_pads[] = {
 520         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 521         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 522         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 523         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 524         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 525         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 526         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 527         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 528         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 529         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 530         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 531         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 532         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 533         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 534 };
 535
 536 static void cm_fx6_setup_gpmi_nand(void)
 537 {
 538         SETUP_IOMUX_PADS(nand_pads);
 539         /* Enable clock roots */
 540         enable_usdhc_clk(1, 3);
 541         enable_usdhc_clk(1, 4);
 542
 543         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
 544                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
 545                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
 546 }
 547 #else
 548 static void cm_fx6_setup_gpmi_nand(void) {}
 549 #endif
 550
 551 #ifdef CONFIG_FSL_ESDHC
 552 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 553         {USDHC1_BASE_ADDR},
 554         {USDHC2_BASE_ADDR},
 555         {USDHC3_BASE_ADDR},
 556 };
 557
 558 static enum mxc_clock usdhc_clk[3] = {
 559         MXC_ESDHC_CLK,
 560         MXC_ESDHC2_CLK,
 561         MXC_ESDHC3_CLK,
 562 };
 563
 564 int board_mmc_init(bd_t *bis)
 565 {
 566         int i;
 567
 568         cm_fx6_set_usdhc_iomux();
 569         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 570                 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
 571                 usdhc_cfg[i].max_bus_width = 4;
 572                 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 573                 enable_usdhc_clk(1, i);
 574         }
 575
 576         return 0;
 577 }
 578 #endif
 579
 580 #ifdef CONFIG_MXC_SPI
 581 int cm_fx6_setup_ecspi(void)
 582 {
 583         cm_fx6_set_ecspi_iomux();
 584         return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
 585 }
 586 #else
 587 int cm_fx6_setup_ecspi(void) { return 0; }
 588 #endif
 589
 590 #ifdef CONFIG_OF_BOARD_SETUP
 591 #define USDHC3_PATH     "/soc/aips-bus@02100000/usdhc@02198000/"
 592
 593 struct node_info nodes[] = {
 594         /*
 595          * Both entries target the same flash chip. The st,m25p compatible
 596          * is used in the vendor device trees, while upstream uses (the
 597          * documented) jedec,spi-nor compatible.
 598          */
 599         { "st,m25p",    MTD_DEV_TYPE_NOR,       },
 600         { "jedec,spi-nor",      MTD_DEV_TYPE_NOR,       },
 601 };
 602
 603 int ft_board_setup(void *blob, bd_t *bd)
 604 {
 605         u32 baseboard_rev;
 606         int nodeoffset;
 607         uint8_t enetaddr[6];
 608         char baseboard_name[16];
 609         int err;
 610
 611         fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */
 612
 613         /* MAC addr */
 614         if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
 615                 fdt_find_and_setprop(blob,
 616                                      "/soc/aips-bus@02100000/ethernet@02188000",
 617                                      "local-mac-address", enetaddr, 6, 1);
 618         }
 619
 620         if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
 621                 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
 622                                      enetaddr, 6, 1);
 623         }
 624
 625         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 626
 627         baseboard_rev = cl_eeprom_get_board_rev(0);
 628         err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
 629         if (err || baseboard_rev == 0)
 630                 return 0; /* Assume not an early revision SB-FX6m baseboard */
 631
 632         if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
 633                 nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
 634                 fdt_delprop(blob, nodeoffset, "cd-gpios");
 635                 fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
 636                                      NULL, 0, 1);
 637                 fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
 638                                      NULL, 0, 1);
 639         }
 640
 641         return 0;
 642 }
 643 #endif
 644
 645 int board_init(void)
 646 {
 647         int ret;
 648
 649         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 650         cm_fx6_setup_gpmi_nand();
 651
 652         ret = cm_fx6_setup_ecspi();
 653         if (ret)
 654                 printf("Warning: ECSPI setup failed: %d\n", ret);
 655
 656         ret = cm_fx6_setup_usb_otg();
 657         if (ret)
 658                 printf("Warning: USB OTG setup failed: %d\n", ret);
 659
 660         ret = cm_fx6_setup_usb_host();
 661         if (ret)
 662                 printf("Warning: USB host setup failed: %d\n", ret);
 663
 664         /*
 665          * cm-fx6 may have iSSD not assembled and in this case it has
 666          * bypasses for a (m)SATA socket on the baseboard. The socketed
 667          * device is not controlled by those GPIOs. So just print a warning
 668          * if the setup fails.
 669          */
 670         ret = cm_fx6_setup_issd();
 671         if (ret)
 672                 printf("Warning: iSSD setup failed: %d\n", ret);
 673
 674         /* Warn on failure but do not abort boot */
 675         ret = cm_fx6_setup_i2c();
 676         if (ret)
 677                 printf("Warning: I2C setup failed: %d\n", ret);
 678
 679         cm_fx6_setup_display();
 680
 681         /* This should be done in the MMC driver when MX6 has a clock driver */
 682 #ifdef CONFIG_FSL_ESDHC
 683         if (IS_ENABLED(CONFIG_BLK)) {
 684                 int i;
 685
 686                 cm_fx6_set_usdhc_iomux();
 687                 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
 688                         enable_usdhc_clk(1, i);
 689         }
 690 #endif
 691
 692         return 0;
 693 }
 694
 695 int checkboard(void)
 696 {
 697         puts("Board: CM-FX6\n");
 698         return 0;
 699 }
 700
 701 int misc_init_r(void)
 702 {
 703         cl_print_pcb_info();
 704
 705         return 0;
 706 }
 707
 708 int dram_init_banksize(void)
 709 {
 710         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 711         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 712
 713         switch (gd->ram_size) {
 714         case 0x10000000: /* DDR_16BIT_256MB */
 715                 gd->bd->bi_dram[0].size = 0x10000000;
 716                 gd->bd->bi_dram[1].size = 0;
 717                 break;
 718         case 0x20000000: /* DDR_32BIT_512MB */
 719                 gd->bd->bi_dram[0].size = 0x20000000;
 720                 gd->bd->bi_dram[1].size = 0;
 721                 break;
 722         case 0x40000000:
 723                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 724                         gd->bd->bi_dram[0].size = 0x20000000;
 725                         gd->bd->bi_dram[1].size = 0x20000000;
 726                 } else { /* DDR_64BIT_1GB */
 727                         gd->bd->bi_dram[0].size = 0x40000000;
 728                         gd->bd->bi_dram[1].size = 0;
 729                 }
 730                 break;
 731         case 0x80000000: /* DDR_64BIT_2GB */
 732                 gd->bd->bi_dram[0].size = 0x40000000;
 733                 gd->bd->bi_dram[1].size = 0x40000000;
 734                 break;
 735         case 0xEFF00000: /* DDR_64BIT_4GB */
 736                 gd->bd->bi_dram[0].size = 0x70000000;
 737                 gd->bd->bi_dram[1].size = 0x7FF00000;
 738                 break;
 739         }
 740
 741         return 0;
 742 }
 743
 744 int dram_init(void)
 745 {
 746         gd->ram_size = imx_ddr_size();
 747         switch (gd->ram_size) {
 748         case 0x10000000:
 749         case 0x20000000:
 750         case 0x40000000:
 751         case 0x80000000:
 752                 break;
 753         case 0xF0000000:
 754                 gd->ram_size -= 0x100000;
 755                 break;
 756         default:
 757                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 758                 return -1;
 759         }
 760
 761         return 0;
 762 }
 763
 764 u32 get_board_rev(void)
 765 {
 766         return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
 767 }
 768
 769 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
 770         .reg = (struct mxc_uart *)UART4_BASE,
 771 };
 772
 773 U_BOOT_DEVICE(cm_fx6_serial) = {
 774         .name   = "serial_mxc",
 775         .platdata = &cm_fx6_mxc_serial_plat,
 776 };
 777
 778 #if CONFIG_IS_ENABLED(AHCI)
 779 static int sata_imx_probe(struct udevice *dev)
 780 {
 781         int i, err;
 782
 783         /* Make sure this gpio has logical 0 value */
 784         gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 785         udelay(100);
 786         cm_fx6_sata_power(1);
 787
 788         for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
 789                 err = setup_sata();
 790                 if (err) {
 791                         printf("SATA setup failed: %d\n", err);
 792                         return err;
 793                 }
 794
 795                 udelay(100);
 796
 797                 err = dwc_ahsata_probe(dev);
 798                 if (!err)
 799                         break;
 800
 801                 /* There is no device on the SATA port */
 802                 if (sata_dm_port_status(0, 0) == 0)
 803                         break;
 804
 805                 /* There's a device, but link not established. Retry */
 806                 device_remove(dev, DM_REMOVE_NORMAL);
 807         }
 808
 809         return 0;
 810 }
 811
 812 static int sata_imx_remove(struct udevice *dev)
 813 {
 814         cm_fx6_sata_power(0);
 815         mdelay(250);
 816
 817         return 0;
 818 }
 819
 820 struct ahci_ops sata_imx_ops = {
 821         .port_status = dwc_ahsata_port_status,
 822         .reset  = dwc_ahsata_bus_reset,
 823         .scan   = dwc_ahsata_scan,
 824 };
 825
 826 static const struct udevice_id sata_imx_ids[] = {
 827         { .compatible = "fsl,imx6q-ahci" },
 828         { }
 829 };
 830
 831 U_BOOT_DRIVER(sata_imx) = {
 832         .name           = "dwc_ahci",
 833         .id             = UCLASS_AHCI,
 834         .of_match       = sata_imx_ids,
 835         .ops            = &sata_imx_ops,
 836         .probe          = sata_imx_probe,
 837         .remove         = sata_imx_remove,  /* reset bus to stop it */
 838 };
 839 #endif /* AHCI */