2 * Board functions for Compulab CM-FX6 board
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
6 * Author: Nikita Kiryanov <nikita@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <fsl_esdhc.h>
16 #include <fdt_support.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/arch/iomux.h>
21 #include <asm/imx-common/mxc_i2c.h>
22 #include <asm/imx-common/sata.h>
25 #include <dm/platform_data/serial_mxc.h>
27 #include "../common/eeprom.h"
29 DECLARE_GLOBAL_DATA_PTR
;
31 #ifdef CONFIG_DWC_AHSATA
32 static int cm_fx6_issd_gpios
[] = {
33 /* The order of the GPIOs in the array is important! */
38 CM_FX6_SATA_NSTANDBY1
,
39 CM_FX6_SATA_NSTANDBY2
,
42 static void cm_fx6_sata_power(int on
)
46 if (!on
) { /* tell the iSSD that the power will be removed */
47 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT
, 1);
51 for (i
= 0; i
< ARRAY_SIZE(cm_fx6_issd_gpios
); i
++) {
52 gpio_direction_output(cm_fx6_issd_gpios
[i
], on
);
56 if (!on
) /* for compatibility lower the power loss interrupt */
57 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT
, 0);
60 static iomux_v3_cfg_t
const sata_pads
[] = {
62 IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
63 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
64 IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
65 IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
67 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
68 IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
69 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
70 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
71 IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
74 static int cm_fx6_setup_issd(void)
78 SETUP_IOMUX_PADS(sata_pads
);
80 for (i
= 0; i
< ARRAY_SIZE(cm_fx6_issd_gpios
); i
++) {
81 ret
= gpio_request(cm_fx6_issd_gpios
[i
], "sata");
86 ret
= gpio_request(CM_FX6_SATA_PWLOSS_INT
, "sata_pwloss_int");
93 #define CM_FX6_SATA_INIT_RETRIES 10
94 int sata_initialize(void)
98 /* Make sure this gpio has logical 0 value */
99 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT
, 0);
101 cm_fx6_sata_power(1);
103 for (i
= 0; i
< CM_FX6_SATA_INIT_RETRIES
; i
++) {
106 printf("SATA setup failed: %d\n", err
);
112 err
= __sata_initialize();
116 /* There is no device on the SATA port */
117 if (sata_port_status(0, 0) == 0)
120 /* There's a device, but link not established. Retry */
129 cm_fx6_sata_power(0);
135 static int cm_fx6_setup_issd(void) { return 0; }
138 #ifdef CONFIG_SYS_I2C_MXC
139 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
140 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
141 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
144 PAD_EIM_D21__I2C1_SCL
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
145 PAD_EIM_D21__GPIO3_IO21
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
147 PAD_EIM_D28__I2C1_SDA
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
148 PAD_EIM_D28__GPIO3_IO28
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
152 PAD_KEY_COL3__I2C2_SCL
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
153 PAD_KEY_COL3__GPIO4_IO12
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
155 PAD_KEY_ROW3__I2C2_SDA
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
156 PAD_KEY_ROW3__GPIO4_IO13
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
160 PAD_GPIO_3__I2C3_SCL
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
161 PAD_GPIO_3__GPIO1_IO03
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
163 PAD_GPIO_6__I2C3_SDA
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
164 PAD_GPIO_6__GPIO1_IO06
| MUX_PAD_CTRL(I2C_PAD_CTRL
),
168 static int cm_fx6_setup_one_i2c(int busnum
, struct i2c_pads_info
*pads
)
172 ret
= setup_i2c(busnum
, CONFIG_SYS_I2C_SPEED
, 0x7f, pads
);
174 printf("Warning: I2C%d setup failed: %d\n", busnum
, ret
);
179 static int cm_fx6_setup_i2c(void)
183 /* i2c<x>_pads are wierd macro variables; we can't use an array */
184 err
= cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads
));
187 err
= cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads
));
190 err
= cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads
));
197 static int cm_fx6_setup_i2c(void) { return 0; }
200 #ifdef CONFIG_USB_EHCI_MX6
201 #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
202 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
203 PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
204 #define MX6_USBNC_BASEADDR 0x2184800
205 #define USBNC_USB_H1_PWR_POL (1 << 9)
207 static int cm_fx6_setup_usb_host(void)
211 err
= gpio_request(CM_FX6_USB_HUB_RST
, "usb hub rst");
215 SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR
| MUX_PAD_CTRL(NO_PAD_CTRL
));
216 SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08
| MUX_PAD_CTRL(NO_PAD_CTRL
));
221 static int cm_fx6_setup_usb_otg(void)
224 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
226 err
= gpio_request(SB_FX6_USB_OTG_PWR
, "usb-pwr");
228 printf("USB OTG pwr gpio request failed: %d\n", err
);
232 SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22
| MUX_PAD_CTRL(NO_PAD_CTRL
));
233 SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID
|
234 MUX_PAD_CTRL(WEAK_PULLDOWN
));
235 clrbits_le32(&iomux
->gpr
[1], IOMUXC_GPR1_OTG_ID_MASK
);
236 /* disable ext. charger detect, or it'll affect signal quality at dp. */
237 return gpio_direction_output(SB_FX6_USB_OTG_PWR
, 0);
240 int board_ehci_hcd_init(int port
)
243 u32
*usbnc_usb_uh1_ctrl
= (u32
*)(MX6_USBNC_BASEADDR
+ 4);
245 /* Only 1 host controller in use. port 0 is OTG & needs no attention */
249 /* Set PWR polarity to match power switch's enable polarity */
250 setbits_le32(usbnc_usb_uh1_ctrl
, USBNC_USB_H1_PWR_POL
);
251 ret
= gpio_direction_output(CM_FX6_USB_HUB_RST
, 0);
256 ret
= gpio_direction_output(CM_FX6_USB_HUB_RST
, 1);
265 int board_ehci_power(int port
, int on
)
268 return gpio_direction_output(SB_FX6_USB_OTG_PWR
, on
);
273 static int cm_fx6_setup_usb_otg(void) { return 0; }
274 static int cm_fx6_setup_usb_host(void) { return 0; }
277 #ifdef CONFIG_FEC_MXC
278 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
279 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
281 static int mx6_rgmii_rework(struct phy_device
*phydev
)
285 /* Ar8031 phy SmartEEE feature cause link status generates glitch,
286 * which cause ethernet link down/up issue, so disable SmartEEE
288 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xd, 0x3);
289 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xe, 0x805d);
290 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xd, 0x4003);
291 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, 0xe);
293 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xe, val
);
295 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
296 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xd, 0x7);
297 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xe, 0x8016);
298 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xd, 0x4007);
300 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, 0xe);
303 phy_write(phydev
, MDIO_DEVAD_NONE
, 0xe, val
);
305 /* introduce tx clock delay */
306 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1d, 0x5);
307 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, 0x1e);
309 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, val
);
314 int board_phy_config(struct phy_device
*phydev
)
316 mx6_rgmii_rework(phydev
);
318 if (phydev
->drv
->config
)
319 return phydev
->drv
->config(phydev
);
324 static iomux_v3_cfg_t
const enet_pads
[] = {
325 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
326 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
327 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
328 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
329 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
330 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
331 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
332 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
333 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
334 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
335 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
336 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
337 IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
338 IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
339 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08
| MUX_PAD_CTRL(0x84)),
340 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
|
341 MUX_PAD_CTRL(ENET_PAD_CTRL
)),
342 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
|
343 MUX_PAD_CTRL(ENET_PAD_CTRL
)),
344 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
|
345 MUX_PAD_CTRL(ENET_PAD_CTRL
)),
348 static int handle_mac_address(void)
350 unsigned char enetaddr
[6];
353 rc
= eth_getenv_enetaddr("ethaddr", enetaddr
);
357 rc
= cl_eeprom_read_mac_addr(enetaddr
);
361 if (!is_valid_ether_addr(enetaddr
))
364 return eth_setenv_enetaddr("ethaddr", enetaddr
);
367 int board_eth_init(bd_t
*bis
)
371 err
= handle_mac_address();
373 puts("No MAC address found\n");
375 SETUP_IOMUX_PADS(enet_pads
);
377 err
= gpio_request(CM_FX6_ENET_NRST
, "enet_nrst");
379 printf("Etnernet NRST gpio request failed: %d\n", err
);
380 gpio_direction_output(CM_FX6_ENET_NRST
, 0);
382 gpio_set_value(CM_FX6_ENET_NRST
, 1);
384 return cpu_eth_init(bis
);
388 #ifdef CONFIG_NAND_MXS
389 static iomux_v3_cfg_t
const nand_pads
[] = {
390 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
391 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
392 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
393 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
394 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
395 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
396 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
397 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
398 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
399 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
400 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
401 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
402 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
403 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
406 static void cm_fx6_setup_gpmi_nand(void)
408 SETUP_IOMUX_PADS(nand_pads
);
409 /* Enable clock roots */
410 enable_usdhc_clk(1, 3);
411 enable_usdhc_clk(1, 4);
413 setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
414 MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
415 MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
418 static void cm_fx6_setup_gpmi_nand(void) {}
421 #ifdef CONFIG_FSL_ESDHC
422 static struct fsl_esdhc_cfg usdhc_cfg
[3] = {
428 static enum mxc_clock usdhc_clk
[3] = {
434 int board_mmc_init(bd_t
*bis
)
438 cm_fx6_set_usdhc_iomux();
439 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
440 usdhc_cfg
[i
].sdhc_clk
= mxc_get_clock(usdhc_clk
[i
]);
441 usdhc_cfg
[i
].max_bus_width
= 4;
442 fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
443 enable_usdhc_clk(1, i
);
450 #ifdef CONFIG_MXC_SPI
451 int cm_fx6_setup_ecspi(void)
453 cm_fx6_set_ecspi_iomux();
454 return gpio_request(CM_FX6_ECSPI_BUS0_CS0
, "ecspi_bus0_cs0");
457 int cm_fx6_setup_ecspi(void) { return 0; }
460 #ifdef CONFIG_OF_BOARD_SETUP
461 int ft_board_setup(void *blob
, bd_t
*bd
)
466 if (eth_getenv_enetaddr("ethaddr", enetaddr
)) {
467 fdt_find_and_setprop(blob
,
468 "/soc/aips-bus@02100000/ethernet@02188000",
469 "local-mac-address", enetaddr
, 6, 1);
480 gd
->bd
->bi_boot_params
= PHYS_SDRAM_1
+ 0x100;
481 cm_fx6_setup_gpmi_nand();
483 ret
= cm_fx6_setup_ecspi();
485 printf("Warning: ECSPI setup failed: %d\n", ret
);
487 ret
= cm_fx6_setup_usb_otg();
489 printf("Warning: USB OTG setup failed: %d\n", ret
);
491 ret
= cm_fx6_setup_usb_host();
493 printf("Warning: USB host setup failed: %d\n", ret
);
496 * cm-fx6 may have iSSD not assembled and in this case it has
497 * bypasses for a (m)SATA socket on the baseboard. The socketed
498 * device is not controlled by those GPIOs. So just print a warning
499 * if the setup fails.
501 ret
= cm_fx6_setup_issd();
503 printf("Warning: iSSD setup failed: %d\n", ret
);
505 /* Warn on failure but do not abort boot */
506 ret
= cm_fx6_setup_i2c();
508 printf("Warning: I2C setup failed: %d\n", ret
);
515 puts("Board: CM-FX6\n");
519 void dram_init_banksize(void)
521 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM_1
;
522 gd
->bd
->bi_dram
[1].start
= PHYS_SDRAM_2
;
524 switch (gd
->ram_size
) {
525 case 0x10000000: /* DDR_16BIT_256MB */
526 gd
->bd
->bi_dram
[0].size
= 0x10000000;
527 gd
->bd
->bi_dram
[1].size
= 0;
529 case 0x20000000: /* DDR_32BIT_512MB */
530 gd
->bd
->bi_dram
[0].size
= 0x20000000;
531 gd
->bd
->bi_dram
[1].size
= 0;
534 if (is_cpu_type(MXC_CPU_MX6SOLO
)) { /* DDR_32BIT_1GB */
535 gd
->bd
->bi_dram
[0].size
= 0x20000000;
536 gd
->bd
->bi_dram
[1].size
= 0x20000000;
537 } else { /* DDR_64BIT_1GB */
538 gd
->bd
->bi_dram
[0].size
= 0x40000000;
539 gd
->bd
->bi_dram
[1].size
= 0;
542 case 0x80000000: /* DDR_64BIT_2GB */
543 gd
->bd
->bi_dram
[0].size
= 0x40000000;
544 gd
->bd
->bi_dram
[1].size
= 0x40000000;
546 case 0xEFF00000: /* DDR_64BIT_4GB */
547 gd
->bd
->bi_dram
[0].size
= 0x70000000;
548 gd
->bd
->bi_dram
[1].size
= 0x7FF00000;
555 gd
->ram_size
= imx_ddr_size();
556 switch (gd
->ram_size
) {
563 gd
->ram_size
-= 0x100000;
566 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd
->ram_size
);
573 u32
get_board_rev(void)
575 return cl_eeprom_get_board_rev();
578 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat
= {
579 .reg
= (struct mxc_uart
*)UART4_BASE
,
582 U_BOOT_DEVICE(cm_fx6_serial
) = {
583 .name
= "serial_mxc",
584 .platdata
= &cm_fx6_mxc_serial_plat
,