board/compulab/cm_fx6/cm_fx6.c

   1 /*
   2  * Board functions for Compulab CM-FX6 board
   3  *
   4  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <fsl_esdhc.h>
  14 #include <miiphy.h>
  15 #include <netdev.h>
  16 #include <fdt_support.h>
  17 #include <sata.h>
  18 #include <splash.h>
  19 #include <asm/arch/crm_regs.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/arch/iomux.h>
  22 #include <asm/arch/mxc_hdmi.h>
  23 #include <asm/imx-common/mxc_i2c.h>
  24 #include <asm/imx-common/sata.h>
  25 #include <asm/imx-common/video.h>
  26 #include <asm/io.h>
  27 #include <asm/gpio.h>
  28 #include <dm/platform_data/serial_mxc.h>
  29 #include "common.h"
  30 #include "../common/eeprom.h"
  31 #include "../common/common.h"
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #ifdef CONFIG_SPLASH_SCREEN
  36 static struct splash_location cm_fx6_splash_locations[] = {
  37         {
  38                 .name = "sf",
  39                 .storage = SPLASH_STORAGE_SF,
  40                 .offset = 0x100000,
  41         },
  42 };
  43
  44 int splash_screen_prepare(void)
  45 {
  46         return splash_source_load(cm_fx6_splash_locations,
  47                                   ARRAY_SIZE(cm_fx6_splash_locations));
  48 }
  49 #endif
  50
  51 #ifdef CONFIG_IMX_HDMI
  52 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
  53 {
  54         imx_enable_hdmi_phy();
  55 }
  56
  57 struct display_info_t const displays[] = {
  58         {
  59                 .bus    = -1,
  60                 .addr   = 0,
  61                 .pixfmt = IPU_PIX_FMT_RGB24,
  62                 .detect = detect_hdmi,
  63                 .enable = cm_fx6_enable_hdmi,
  64                 .mode   = {
  65                         .name           = "HDMI",
  66                         .refresh        = 60,
  67                         .xres           = 1024,
  68                         .yres           = 768,
  69                         .pixclock       = 40385,
  70                         .left_margin    = 220,
  71                         .right_margin   = 40,
  72                         .upper_margin   = 21,
  73                         .lower_margin   = 7,
  74                         .hsync_len      = 60,
  75                         .vsync_len      = 10,
  76                         .sync           = FB_SYNC_EXT,
  77                         .vmode          = FB_VMODE_NONINTERLACED,
  78                 }
  79         },
  80 };
  81 size_t display_count = ARRAY_SIZE(displays);
  82
  83 static void cm_fx6_setup_display(void)
  84 {
  85         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  86         int reg;
  87
  88         enable_ipu_clock();
  89         imx_setup_hdmi();
  90         reg = __raw_readl(&mxc_ccm->CCGR3);
  91         reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK;
  92         writel(reg, &mxc_ccm->CCGR3);
  93 }
  94 #else
  95 static inline void cm_fx6_setup_display(void) {}
  96 #endif /* CONFIG_VIDEO_IPUV3 */
  97
  98 #ifdef CONFIG_DWC_AHSATA
  99 static int cm_fx6_issd_gpios[] = {
 100         /* The order of the GPIOs in the array is important! */
 101         CM_FX6_SATA_LDO_EN,
 102         CM_FX6_SATA_PHY_SLP,
 103         CM_FX6_SATA_NRSTDLY,
 104         CM_FX6_SATA_PWREN,
 105         CM_FX6_SATA_NSTANDBY1,
 106         CM_FX6_SATA_NSTANDBY2,
 107 };
 108
 109 static void cm_fx6_sata_power(int on)
 110 {
 111         int i;
 112
 113         if (!on) { /* tell the iSSD that the power will be removed */
 114                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
 115                 mdelay(10);
 116         }
 117
 118         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 119                 gpio_direction_output(cm_fx6_issd_gpios[i], on);
 120                 udelay(100);
 121         }
 122
 123         if (!on) /* for compatibility lower the power loss interrupt */
 124                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 125 }
 126
 127 static iomux_v3_cfg_t const sata_pads[] = {
 128         /* SATA PWR */
 129         IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 130         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 131         IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 132         IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 133         /* SATA CTRL */
 134         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 135         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 136         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 137         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 138         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 139 };
 140
 141 static int cm_fx6_setup_issd(void)
 142 {
 143         int ret, i;
 144
 145         SETUP_IOMUX_PADS(sata_pads);
 146
 147         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 148                 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
 149                 if (ret)
 150                         return ret;
 151         }
 152
 153         ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
 154         if (ret)
 155                 return ret;
 156
 157         return 0;
 158 }
 159
 160 #define CM_FX6_SATA_INIT_RETRIES        10
 161 int sata_initialize(void)
 162 {
 163         int err, i;
 164
 165         /* Make sure this gpio has logical 0 value */
 166         gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 167         udelay(100);
 168         cm_fx6_sata_power(1);
 169
 170         for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
 171                 err = setup_sata();
 172                 if (err) {
 173                         printf("SATA setup failed: %d\n", err);
 174                         return err;
 175                 }
 176
 177                 udelay(100);
 178
 179                 err = __sata_initialize();
 180                 if (!err)
 181                         break;
 182
 183                 /* There is no device on the SATA port */
 184                 if (sata_port_status(0, 0) == 0)
 185                         break;
 186
 187                 /* There's a device, but link not established. Retry */
 188         }
 189
 190         return err;
 191 }
 192
 193 int sata_stop(void)
 194 {
 195         __sata_stop();
 196         cm_fx6_sata_power(0);
 197         mdelay(250);
 198
 199         return 0;
 200 }
 201 #else
 202 static int cm_fx6_setup_issd(void) { return 0; }
 203 #endif
 204
 205 #ifdef CONFIG_SYS_I2C_MXC
 206 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 207                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
 208                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 209
 210 I2C_PADS(i2c0_pads,
 211          PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 212          PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 213          IMX_GPIO_NR(3, 21),
 214          PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 215          PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 216          IMX_GPIO_NR(3, 28));
 217
 218 I2C_PADS(i2c1_pads,
 219          PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 220          PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 221          IMX_GPIO_NR(4, 12),
 222          PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 223          PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 224          IMX_GPIO_NR(4, 13));
 225
 226 I2C_PADS(i2c2_pads,
 227          PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 228          PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 229          IMX_GPIO_NR(1, 3),
 230          PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 231          PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 232          IMX_GPIO_NR(1, 6));
 233
 234
 235 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
 236 {
 237         int ret;
 238
 239         ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
 240         if (ret)
 241                 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
 242
 243         return ret;
 244 }
 245
 246 static int cm_fx6_setup_i2c(void)
 247 {
 248         int ret = 0, err;
 249
 250         /* i2c<x>_pads are wierd macro variables; we can't use an array */
 251         err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
 252         if (err)
 253                 ret = err;
 254         err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
 255         if (err)
 256                 ret = err;
 257         err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
 258         if (err)
 259                 ret = err;
 260
 261         return ret;
 262 }
 263 #else
 264 static int cm_fx6_setup_i2c(void) { return 0; }
 265 #endif
 266
 267 #ifdef CONFIG_USB_EHCI_MX6
 268 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
 269                         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 270                         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 271 #define MX6_USBNC_BASEADDR      0x2184800
 272 #define USBNC_USB_H1_PWR_POL    (1 << 9)
 273
 274 static int cm_fx6_setup_usb_host(void)
 275 {
 276         int err;
 277
 278         err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
 279         if (err)
 280                 return err;
 281
 282         SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
 283         SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
 284
 285         return 0;
 286 }
 287
 288 static int cm_fx6_setup_usb_otg(void)
 289 {
 290         int err;
 291         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 292
 293         err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
 294         if (err) {
 295                 printf("USB OTG pwr gpio request failed: %d\n", err);
 296                 return err;
 297         }
 298
 299         SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
 300         SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
 301                                                 MUX_PAD_CTRL(WEAK_PULLDOWN));
 302         clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
 303         /* disable ext. charger detect, or it'll affect signal quality at dp. */
 304         return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 305 }
 306
 307 int board_ehci_hcd_init(int port)
 308 {
 309         int ret;
 310         u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 311
 312         /* Only 1 host controller in use. port 0 is OTG & needs no attention */
 313         if (port != 1)
 314                 return 0;
 315
 316         /* Set PWR polarity to match power switch's enable polarity */
 317         setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
 318         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
 319         if (ret)
 320                 return ret;
 321
 322         udelay(10);
 323         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
 324         if (ret)
 325                 return ret;
 326
 327         mdelay(1);
 328
 329         return 0;
 330 }
 331
 332 int board_ehci_power(int port, int on)
 333 {
 334         if (port == 0)
 335                 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
 336
 337         return 0;
 338 }
 339 #else
 340 static int cm_fx6_setup_usb_otg(void) { return 0; }
 341 static int cm_fx6_setup_usb_host(void) { return 0; }
 342 #endif
 343
 344 #ifdef CONFIG_FEC_MXC
 345 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 346                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 347
 348 static int mx6_rgmii_rework(struct phy_device *phydev)
 349 {
 350         unsigned short val;
 351
 352         /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 353          * which cause ethernet link down/up issue, so disable SmartEEE
 354          */
 355         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 356         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 357         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 358         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 359         val &= ~(0x1 << 8);
 360         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 361
 362         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 363         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 364         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 365         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 366
 367         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 368         val &= 0xffe3;
 369         val |= 0x18;
 370         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 371
 372         /* introduce tx clock delay */
 373         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 374         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 375         val |= 0x0100;
 376         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 377
 378         return 0;
 379 }
 380
 381 int board_phy_config(struct phy_device *phydev)
 382 {
 383         mx6_rgmii_rework(phydev);
 384
 385         if (phydev->drv->config)
 386                 return phydev->drv->config(phydev);
 387
 388         return 0;
 389 }
 390
 391 static iomux_v3_cfg_t const enet_pads[] = {
 392         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 393         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 394         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 395         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 396         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 397         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 398         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 399         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 400         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 401         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 402         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 403         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 404         IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 405         IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 406         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
 407         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
 408                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 409         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 410                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 411         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 412                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 413 };
 414
 415 static int handle_mac_address(char *env_var, uint eeprom_bus)
 416 {
 417         unsigned char enetaddr[6];
 418         int rc;
 419
 420         rc = eth_getenv_enetaddr(env_var, enetaddr);
 421         if (rc)
 422                 return 0;
 423
 424         rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
 425         if (rc)
 426                 return rc;
 427
 428         if (!is_valid_ethaddr(enetaddr))
 429                 return -1;
 430
 431         return eth_setenv_enetaddr(env_var, enetaddr);
 432 }
 433
 434 #define SB_FX6_I2C_EEPROM_BUS   0
 435 #define NO_MAC_ADDR             "No MAC address found for %s\n"
 436 int board_eth_init(bd_t *bis)
 437 {
 438         int err;
 439
 440         if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
 441                 printf(NO_MAC_ADDR, "primary NIC");
 442
 443         if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
 444                 printf(NO_MAC_ADDR, "secondary NIC");
 445
 446         SETUP_IOMUX_PADS(enet_pads);
 447         /* phy reset */
 448         err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
 449         if (err)
 450                 printf("Etnernet NRST gpio request failed: %d\n", err);
 451         gpio_direction_output(CM_FX6_ENET_NRST, 0);
 452         udelay(500);
 453         gpio_set_value(CM_FX6_ENET_NRST, 1);
 454         enable_enet_clk(1);
 455         return cpu_eth_init(bis);
 456 }
 457 #endif
 458
 459 #ifdef CONFIG_NAND_MXS
 460 static iomux_v3_cfg_t const nand_pads[] = {
 461         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 462         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 463         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 464         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 465         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 466         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 467         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 468         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 469         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 470         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 471         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 472         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 473         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 474         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 475 };
 476
 477 static void cm_fx6_setup_gpmi_nand(void)
 478 {
 479         SETUP_IOMUX_PADS(nand_pads);
 480         /* Enable clock roots */
 481         enable_usdhc_clk(1, 3);
 482         enable_usdhc_clk(1, 4);
 483
 484         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
 485                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
 486                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
 487 }
 488 #else
 489 static void cm_fx6_setup_gpmi_nand(void) {}
 490 #endif
 491
 492 #ifdef CONFIG_FSL_ESDHC
 493 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 494         {USDHC1_BASE_ADDR},
 495         {USDHC2_BASE_ADDR},
 496         {USDHC3_BASE_ADDR},
 497 };
 498
 499 static enum mxc_clock usdhc_clk[3] = {
 500         MXC_ESDHC_CLK,
 501         MXC_ESDHC2_CLK,
 502         MXC_ESDHC3_CLK,
 503 };
 504
 505 int board_mmc_init(bd_t *bis)
 506 {
 507         int i;
 508
 509         cm_fx6_set_usdhc_iomux();
 510         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 511                 usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
 512                 usdhc_cfg[i].max_bus_width = 4;
 513                 fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 514                 enable_usdhc_clk(1, i);
 515         }
 516
 517         return 0;
 518 }
 519 #endif
 520
 521 #ifdef CONFIG_MXC_SPI
 522 int cm_fx6_setup_ecspi(void)
 523 {
 524         cm_fx6_set_ecspi_iomux();
 525         return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
 526 }
 527 #else
 528 int cm_fx6_setup_ecspi(void) { return 0; }
 529 #endif
 530
 531 #ifdef CONFIG_OF_BOARD_SETUP
 532 int ft_board_setup(void *blob, bd_t *bd)
 533 {
 534         uint8_t enetaddr[6];
 535
 536         /* MAC addr */
 537         if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
 538                 fdt_find_and_setprop(blob,
 539                                      "/soc/aips-bus@02100000/ethernet@02188000",
 540                                      "local-mac-address", enetaddr, 6, 1);
 541         }
 542
 543         if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
 544                 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
 545                                      enetaddr, 6, 1);
 546         }
 547
 548         return 0;
 549 }
 550 #endif
 551
 552 int board_init(void)
 553 {
 554         int ret;
 555
 556         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 557         cm_fx6_setup_gpmi_nand();
 558
 559         ret = cm_fx6_setup_ecspi();
 560         if (ret)
 561                 printf("Warning: ECSPI setup failed: %d\n", ret);
 562
 563         ret = cm_fx6_setup_usb_otg();
 564         if (ret)
 565                 printf("Warning: USB OTG setup failed: %d\n", ret);
 566
 567         ret = cm_fx6_setup_usb_host();
 568         if (ret)
 569                 printf("Warning: USB host setup failed: %d\n", ret);
 570
 571         /*
 572          * cm-fx6 may have iSSD not assembled and in this case it has
 573          * bypasses for a (m)SATA socket on the baseboard. The socketed
 574          * device is not controlled by those GPIOs. So just print a warning
 575          * if the setup fails.
 576          */
 577         ret = cm_fx6_setup_issd();
 578         if (ret)
 579                 printf("Warning: iSSD setup failed: %d\n", ret);
 580
 581         /* Warn on failure but do not abort boot */
 582         ret = cm_fx6_setup_i2c();
 583         if (ret)
 584                 printf("Warning: I2C setup failed: %d\n", ret);
 585
 586         cm_fx6_setup_display();
 587
 588         return 0;
 589 }
 590
 591 int checkboard(void)
 592 {
 593         puts("Board: CM-FX6\n");
 594         return 0;
 595 }
 596
 597 void dram_init_banksize(void)
 598 {
 599         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 600         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 601
 602         switch (gd->ram_size) {
 603         case 0x10000000: /* DDR_16BIT_256MB */
 604                 gd->bd->bi_dram[0].size = 0x10000000;
 605                 gd->bd->bi_dram[1].size = 0;
 606                 break;
 607         case 0x20000000: /* DDR_32BIT_512MB */
 608                 gd->bd->bi_dram[0].size = 0x20000000;
 609                 gd->bd->bi_dram[1].size = 0;
 610                 break;
 611         case 0x40000000:
 612                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 613                         gd->bd->bi_dram[0].size = 0x20000000;
 614                         gd->bd->bi_dram[1].size = 0x20000000;
 615                 } else { /* DDR_64BIT_1GB */
 616                         gd->bd->bi_dram[0].size = 0x40000000;
 617                         gd->bd->bi_dram[1].size = 0;
 618                 }
 619                 break;
 620         case 0x80000000: /* DDR_64BIT_2GB */
 621                 gd->bd->bi_dram[0].size = 0x40000000;
 622                 gd->bd->bi_dram[1].size = 0x40000000;
 623                 break;
 624         case 0xEFF00000: /* DDR_64BIT_4GB */
 625                 gd->bd->bi_dram[0].size = 0x70000000;
 626                 gd->bd->bi_dram[1].size = 0x7FF00000;
 627                 break;
 628         }
 629 }
 630
 631 int dram_init(void)
 632 {
 633         gd->ram_size = imx_ddr_size();
 634         switch (gd->ram_size) {
 635         case 0x10000000:
 636         case 0x20000000:
 637         case 0x40000000:
 638         case 0x80000000:
 639                 break;
 640         case 0xF0000000:
 641                 gd->ram_size -= 0x100000;
 642                 break;
 643         default:
 644                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 645                 return -1;
 646         }
 647
 648         return 0;
 649 }
 650
 651 u32 get_board_rev(void)
 652 {
 653         return cl_eeprom_get_board_rev();
 654 }
 655
 656 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
 657         .reg = (struct mxc_uart *)UART4_BASE,
 658 };
 659
 660 U_BOOT_DEVICE(cm_fx6_serial) = {
 661         .name   = "serial_mxc",
 662         .platdata = &cm_fx6_mxc_serial_plat,
 663 };