2 * SPL specific code for Compulab CM-FX6 board
4 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
6 * Author: Nikita Kiryanov <nikita@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/mx6-ddr.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/crm_regs.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <fsl_esdhc.h>
23 DECLARE_GLOBAL_DATA_PTR
;
36 * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
37 * Freescale QRM, but this is exactly the value used by the automatic
38 * calibration script and it works also in all our tests, so we leave
39 * it as is at this point.
41 #define CM_FX6_DDR_IOMUX_CFG \
42 .dram_sdqs0 = 0x00000038, \
43 .dram_sdqs1 = 0x00000038, \
44 .dram_sdqs2 = 0x00000038, \
45 .dram_sdqs3 = 0x00000038, \
46 .dram_sdqs4 = 0x00000038, \
47 .dram_sdqs5 = 0x00000038, \
48 .dram_sdqs6 = 0x00000038, \
49 .dram_sdqs7 = 0x00000038, \
50 .dram_dqm0 = 0x00000038, \
51 .dram_dqm1 = 0x00000038, \
52 .dram_dqm2 = 0x00000038, \
53 .dram_dqm3 = 0x00000038, \
54 .dram_dqm4 = 0x00000038, \
55 .dram_dqm5 = 0x00000038, \
56 .dram_dqm6 = 0x00000038, \
57 .dram_dqm7 = 0x00000038, \
58 .dram_cas = 0x00000038, \
59 .dram_ras = 0x00000038, \
60 .dram_sdclk_0 = 0x00000038, \
61 .dram_sdclk_1 = 0x00000038, \
62 .dram_sdcke0 = 0x00003000, \
63 .dram_sdcke1 = 0x00003000, \
64 .dram_reset = 0x00000038, \
65 .dram_sdba2 = 0x00000000, \
66 .dram_sdodt0 = 0x00000038, \
67 .dram_sdodt1 = 0x00000038,
69 #define CM_FX6_GPR_IOMUX_CFG \
70 .grp_b0ds = 0x00000038, \
71 .grp_b1ds = 0x00000038, \
72 .grp_b2ds = 0x00000038, \
73 .grp_b3ds = 0x00000038, \
74 .grp_b4ds = 0x00000038, \
75 .grp_b5ds = 0x00000038, \
76 .grp_b6ds = 0x00000038, \
77 .grp_b7ds = 0x00000038, \
78 .grp_addds = 0x00000038, \
79 .grp_ddrmode_ctl = 0x00020000, \
80 .grp_ddrpke = 0x00000000, \
81 .grp_ddrmode = 0x00020000, \
82 .grp_ctlds = 0x00000038, \
83 .grp_ddr_type = 0x000C0000,
85 static struct mx6sdl_iomux_ddr_regs ddr_iomux_s
= { CM_FX6_DDR_IOMUX_CFG
};
86 static struct mx6sdl_iomux_grp_regs grp_iomux_s
= { CM_FX6_GPR_IOMUX_CFG
};
87 static struct mx6dq_iomux_ddr_regs ddr_iomux_q
= { CM_FX6_DDR_IOMUX_CFG
};
88 static struct mx6dq_iomux_grp_regs grp_iomux_q
= { CM_FX6_GPR_IOMUX_CFG
};
90 static struct mx6_mmdc_calibration cm_fx6_calib_s
= {
91 .p0_mpwldectrl0
= 0x005B0061,
92 .p0_mpwldectrl1
= 0x004F0055,
93 .p0_mpdgctrl0
= 0x0314030C,
94 .p0_mpdgctrl1
= 0x025C0268,
95 .p0_mprddlctl
= 0x42464646,
96 .p0_mpwrdlctl
= 0x36322C34,
99 static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s
= {
112 static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s
= {
124 static void spl_mx6s_dram_init(enum ddr_config dram_config
, bool reset
)
127 ((struct mmdc_p_regs
*)MX6_MMDC_P0_MDCTL
)->mdmisc
= 2;
129 switch (dram_config
) {
130 case DDR_16BIT_256MB
:
131 cm_fx6_sysinfo_s
.dsize
= 0;
132 cm_fx6_sysinfo_s
.ncs
= 1;
134 case DDR_32BIT_512MB
:
135 cm_fx6_sysinfo_s
.dsize
= 1;
136 cm_fx6_sysinfo_s
.ncs
= 1;
139 cm_fx6_sysinfo_s
.dsize
= 1;
140 cm_fx6_sysinfo_s
.ncs
= 2;
143 puts("Tried to setup invalid DDR configuration\n");
147 mx6_dram_cfg(&cm_fx6_sysinfo_s
, &cm_fx6_calib_s
, &cm_fx6_ddr3_cfg_s
);
151 static struct mx6_mmdc_calibration cm_fx6_calib_q
= {
152 .p0_mpwldectrl0
= 0x00630068,
153 .p0_mpwldectrl1
= 0x0068005D,
154 .p0_mpdgctrl0
= 0x04140428,
155 .p0_mpdgctrl1
= 0x037C037C,
156 .p0_mprddlctl
= 0x3C30303A,
157 .p0_mpwrdlctl
= 0x3A344038,
158 .p1_mpwldectrl0
= 0x0035004C,
159 .p1_mpwldectrl1
= 0x00170026,
160 .p1_mpdgctrl0
= 0x0374037C,
161 .p1_mpdgctrl1
= 0x0350032C,
162 .p1_mprddlctl
= 0x30322A3C,
163 .p1_mpwrdlctl
= 0x48304A3E,
166 static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q
= {
177 .refsel
= 1, /* Refresh cycles at 32KHz */
178 .refr
= 7, /* 8 refresh commands per refresh cycle */
181 static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q
= {
193 static void spl_mx6q_dram_init(enum ddr_config dram_config
, bool reset
)
196 ((struct mmdc_p_regs
*)MX6_MMDC_P0_MDCTL
)->mdmisc
= 2;
198 cm_fx6_ddr3_cfg_q
.rowaddr
= 14;
199 switch (dram_config
) {
200 case DDR_16BIT_256MB
:
201 cm_fx6_sysinfo_q
.dsize
= 0;
202 cm_fx6_sysinfo_q
.ncs
= 1;
204 case DDR_32BIT_512MB
:
205 cm_fx6_sysinfo_q
.dsize
= 1;
206 cm_fx6_sysinfo_q
.ncs
= 1;
209 cm_fx6_sysinfo_q
.dsize
= 2;
210 cm_fx6_sysinfo_q
.ncs
= 1;
213 cm_fx6_sysinfo_q
.dsize
= 2;
214 cm_fx6_sysinfo_q
.ncs
= 2;
217 cm_fx6_sysinfo_q
.dsize
= 2;
218 cm_fx6_sysinfo_q
.ncs
= 2;
219 cm_fx6_ddr3_cfg_q
.rowaddr
= 15;
222 puts("Tried to setup invalid DDR configuration\n");
226 mx6_dram_cfg(&cm_fx6_sysinfo_q
, &cm_fx6_calib_q
, &cm_fx6_ddr3_cfg_q
);
230 static int cm_fx6_spl_dram_init(void)
232 unsigned long bank1_size
, bank2_size
;
234 switch (get_cpu_type()) {
235 case MXC_CPU_MX6SOLO
:
236 mx6sdl_dram_iocfg(64, &ddr_iomux_s
, &grp_iomux_s
);
238 spl_mx6s_dram_init(DDR_32BIT_1GB
, false);
239 bank1_size
= get_ram_size((long int *)PHYS_SDRAM_1
, 0x80000000);
240 bank2_size
= get_ram_size((long int *)PHYS_SDRAM_2
, 0x80000000);
241 if (bank1_size
== 0x20000000) {
242 if (bank2_size
== 0x20000000)
245 spl_mx6s_dram_init(DDR_32BIT_512MB
, true);
249 spl_mx6s_dram_init(DDR_16BIT_256MB
, true);
250 bank1_size
= get_ram_size((long int *)PHYS_SDRAM_1
, 0x80000000);
251 if (bank1_size
== 0x10000000)
257 mx6dq_dram_iocfg(64, &ddr_iomux_q
, &grp_iomux_q
);
259 spl_mx6q_dram_init(DDR_64BIT_4GB
, false);
260 bank1_size
= get_ram_size((long int *)PHYS_SDRAM_1
, 0x80000000);
261 if (bank1_size
== 0x80000000)
264 if (bank1_size
== 0x40000000) {
265 bank2_size
= get_ram_size((long int *)PHYS_SDRAM_2
,
267 if (bank2_size
== 0x40000000) {
268 /* Don't do a full reset here */
269 spl_mx6q_dram_init(DDR_64BIT_2GB
, false);
271 spl_mx6q_dram_init(DDR_64BIT_1GB
, true);
277 spl_mx6q_dram_init(DDR_32BIT_512MB
, true);
278 bank1_size
= get_ram_size((long int *)PHYS_SDRAM_1
, 0x80000000);
279 if (bank1_size
== 0x20000000)
282 spl_mx6q_dram_init(DDR_16BIT_256MB
, true);
283 bank1_size
= get_ram_size((long int *)PHYS_SDRAM_1
, 0x80000000);
284 if (bank1_size
== 0x10000000)
293 static iomux_v3_cfg_t
const uart4_pads
[] = {
294 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
295 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
298 static void cm_fx6_setup_uart(void)
300 SETUP_IOMUX_PADS(uart4_pads
);
304 #ifdef CONFIG_SPL_SPI_SUPPORT
305 static void cm_fx6_setup_ecspi(void)
307 cm_fx6_set_ecspi_iomux();
308 enable_spi_clk(1, 0);
311 static void cm_fx6_setup_ecspi(void) { }
314 void board_init_f(ulong dummy
)
316 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
319 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
320 * initializes DMA very early (before all board code), so the only
321 * opportunity we have to initialize APBHDMA clocks is in SPL.
323 setbits_le32(&mxc_ccm
->CCGR0
, MXC_CCM_CCGR0_APBHDMA_MASK
);
324 enable_usdhc_clk(1, 2);
328 cm_fx6_setup_ecspi();
331 preloader_console_init();
332 gpio_direction_output(CM_FX6_GREEN_LED
, 1);
333 if (cm_fx6_spl_dram_init()) {
334 puts("!!!ERROR!!! DRAM detection failed!!!\n");
339 void board_boot_order(u32
*spl_boot_list
)
341 spl_boot_list
[0] = spl_boot_device();
342 switch (spl_boot_list
[0]) {
343 case BOOT_DEVICE_SPI
:
344 spl_boot_list
[1] = BOOT_DEVICE_MMC1
;
346 case BOOT_DEVICE_MMC1
:
347 spl_boot_list
[1] = BOOT_DEVICE_SPI
;
352 #ifdef CONFIG_SPL_MMC_SUPPORT
353 static struct fsl_esdhc_cfg usdhc_cfg
= {
354 .esdhc_base
= USDHC3_BASE_ADDR
,
358 int board_mmc_init(bd_t
*bis
)
360 cm_fx6_set_usdhc_iomux();
362 usdhc_cfg
.sdhc_clk
= mxc_get_clock(MXC_ESDHC3_CLK
);
364 return fsl_esdhc_initialize(bis
, &usdhc_cfg
);