board/compulab/cm_t335/cm_t335.c

   1 /*
   2  * Board functions for Compulab CM-T335 board
   3  *
   4  * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
   5  *
   6  * Author: Ilya Ledvich <ilya@compulab.co.il>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <miiphy.h>
  14 #include <cpsw.h>
  15
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/arch/hardware_am33xx.h>
  18 #include <asm/io.h>
  19 #include <asm/gpio.h>
  20
  21 #include "../common/eeprom.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 /*
  26  * Basic board specific setup.  Pinmux has been handled already.
  27  */
  28 int board_init(void)
  29 {
  30         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  31
  32         gpmc_init();
  33
  34 #if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
  35         status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF);
  36 #endif
  37         return 0;
  38 }
  39
  40 #if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
  41 static void cpsw_control(int enabled)
  42 {
  43         /* VTP can be added here */
  44         return;
  45 }
  46
  47 static struct cpsw_slave_data cpsw_slave = {
  48         .slave_reg_ofs  = 0x208,
  49         .sliver_reg_ofs = 0xd80,
  50         .phy_addr       = 0,
  51         .phy_if         = PHY_INTERFACE_MODE_RGMII,
  52 };
  53
  54 static struct cpsw_platform_data cpsw_data = {
  55         .mdio_base              = CPSW_MDIO_BASE,
  56         .cpsw_base              = CPSW_BASE,
  57         .mdio_div               = 0xff,
  58         .channels               = 8,
  59         .cpdma_reg_ofs          = 0x800,
  60         .slaves                 = 1,
  61         .slave_data             = &cpsw_slave,
  62         .ale_reg_ofs            = 0xd00,
  63         .ale_entries            = 1024,
  64         .host_port_reg_ofs      = 0x108,
  65         .hw_stats_reg_ofs       = 0x900,
  66         .bd_ram_ofs             = 0x2000,
  67         .mac_control            = (1 << 5),
  68         .control                = cpsw_control,
  69         .host_port_num          = 0,
  70         .version                = CPSW_CTRL_VERSION_2,
  71 };
  72
  73 /* PHY reset GPIO */
  74 #define GPIO_PHY_RST            GPIO_PIN(3, 7)
  75
  76 static void board_phy_init(void)
  77 {
  78         gpio_request(GPIO_PHY_RST, "phy_rst");
  79         gpio_direction_output(GPIO_PHY_RST, 0);
  80         mdelay(2);
  81         gpio_set_value(GPIO_PHY_RST, 1);
  82         mdelay(2);
  83 }
  84
  85 static void get_efuse_mac_addr(uchar *enetaddr)
  86 {
  87         uint32_t mac_hi, mac_lo;
  88         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  89
  90         mac_lo = readl(&cdev->macid0l);
  91         mac_hi = readl(&cdev->macid0h);
  92         enetaddr[0] = mac_hi & 0xFF;
  93         enetaddr[1] = (mac_hi & 0xFF00) >> 8;
  94         enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
  95         enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
  96         enetaddr[4] = mac_lo & 0xFF;
  97         enetaddr[5] = (mac_lo & 0xFF00) >> 8;
  98 }
  99
 100 /*
 101  * Routine: handle_mac_address
 102  * Description: prepare MAC address for on-board Ethernet.
 103  */
 104 static int handle_mac_address(void)
 105 {
 106         uchar enetaddr[6];
 107         int rv;
 108
 109         rv = eth_getenv_enetaddr("ethaddr", enetaddr);
 110         if (rv)
 111                 return 0;
 112
 113         rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
 114         if (rv)
 115                 get_efuse_mac_addr(enetaddr);
 116
 117         if (!is_valid_ethaddr(enetaddr))
 118                 return -1;
 119
 120         return eth_setenv_enetaddr("ethaddr", enetaddr);
 121 }
 122
 123 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 124 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 125 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 126 #define AR8051_RGMII_TX_CLK_DLY         0x100
 127
 128 int board_eth_init(bd_t *bis)
 129 {
 130         int rv, n = 0;
 131         const char *devname;
 132         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 133
 134         rv = handle_mac_address();
 135         if (rv)
 136                 printf("No MAC address found!\n");
 137
 138         writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
 139
 140         board_phy_init();
 141
 142         rv = cpsw_register(&cpsw_data);
 143         if (rv < 0)
 144                 printf("Error %d registering CPSW switch\n", rv);
 145         else
 146                 n += rv;
 147
 148         /*
 149          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 150          * operating points.  So we must set the TX clock delay feature
 151          * in the AR8051 PHY.  Since we only support a single ethernet
 152          * device, we only do this for the first instance.
 153          */
 154         devname = miiphy_get_current_dev();
 155
 156         miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 157                      AR8051_DEBUG_RGMII_CLK_DLY_REG);
 158         miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 159                      AR8051_RGMII_TX_CLK_DLY);
 160         return n;
 161 }
 162 #endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */