]>
git.ipfire.org Git - people/ms/u-boot.git/blob - board/compulab/cm_t3517/mux.c
2 * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
4 * Authors: Igor Grinberg <grinberg@compulab.co.il>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/sys_proto.h>
11 #include <asm/arch/mux.h>
14 void set_muxconf_regs(void)
17 MUX_VAL(CP(SDRC_D0
), (IEN
| PTD
| DIS
| M0
));
18 MUX_VAL(CP(SDRC_D1
), (IEN
| PTD
| DIS
| M0
));
19 MUX_VAL(CP(SDRC_D2
), (IEN
| PTD
| DIS
| M0
));
20 MUX_VAL(CP(SDRC_D3
), (IEN
| PTD
| DIS
| M0
));
21 MUX_VAL(CP(SDRC_D4
), (IEN
| PTD
| DIS
| M0
));
22 MUX_VAL(CP(SDRC_D5
), (IEN
| PTD
| DIS
| M0
));
23 MUX_VAL(CP(SDRC_D6
), (IEN
| PTD
| DIS
| M0
));
24 MUX_VAL(CP(SDRC_D7
), (IEN
| PTD
| DIS
| M0
));
25 MUX_VAL(CP(SDRC_D8
), (IEN
| PTD
| DIS
| M0
));
26 MUX_VAL(CP(SDRC_D9
), (IEN
| PTD
| DIS
| M0
));
27 MUX_VAL(CP(SDRC_D10
), (IEN
| PTD
| DIS
| M0
));
28 MUX_VAL(CP(SDRC_D11
), (IEN
| PTD
| DIS
| M0
));
29 MUX_VAL(CP(SDRC_D12
), (IEN
| PTD
| DIS
| M0
));
30 MUX_VAL(CP(SDRC_D13
), (IEN
| PTD
| DIS
| M0
));
31 MUX_VAL(CP(SDRC_D14
), (IEN
| PTD
| DIS
| M0
));
32 MUX_VAL(CP(SDRC_D15
), (IEN
| PTD
| DIS
| M0
));
33 MUX_VAL(CP(SDRC_D16
), (IEN
| PTD
| DIS
| M0
));
34 MUX_VAL(CP(SDRC_D17
), (IEN
| PTD
| DIS
| M0
));
35 MUX_VAL(CP(SDRC_D18
), (IEN
| PTD
| DIS
| M0
));
36 MUX_VAL(CP(SDRC_D19
), (IEN
| PTD
| DIS
| M0
));
37 MUX_VAL(CP(SDRC_D20
), (IEN
| PTD
| DIS
| M0
));
38 MUX_VAL(CP(SDRC_D21
), (IEN
| PTD
| DIS
| M0
));
39 MUX_VAL(CP(SDRC_D22
), (IEN
| PTD
| DIS
| M0
));
40 MUX_VAL(CP(SDRC_D23
), (IEN
| PTD
| DIS
| M0
));
41 MUX_VAL(CP(SDRC_D24
), (IEN
| PTD
| DIS
| M0
));
42 MUX_VAL(CP(SDRC_D25
), (IEN
| PTD
| DIS
| M0
));
43 MUX_VAL(CP(SDRC_D26
), (IEN
| PTD
| DIS
| M0
));
44 MUX_VAL(CP(SDRC_D27
), (IEN
| PTD
| DIS
| M0
));
45 MUX_VAL(CP(SDRC_D28
), (IEN
| PTD
| DIS
| M0
));
46 MUX_VAL(CP(SDRC_D29
), (IEN
| PTD
| DIS
| M0
));
47 MUX_VAL(CP(SDRC_D30
), (IEN
| PTD
| DIS
| M0
));
48 MUX_VAL(CP(SDRC_D31
), (IEN
| PTD
| DIS
| M0
));
49 MUX_VAL(CP(SDRC_CLK
), (IEN
| PTD
| DIS
| M0
));
50 MUX_VAL(CP(SDRC_DQS0
), (IEN
| PTD
| DIS
| M0
));
51 MUX_VAL(CP(SDRC_DQS1
), (IEN
| PTD
| DIS
| M0
));
52 MUX_VAL(CP(SDRC_DQS2
), (IEN
| PTD
| DIS
| M0
));
53 MUX_VAL(CP(SDRC_DQS3
), (IEN
| PTD
| DIS
| M0
));
54 MUX_VAL(CP(SDRC_CKE0
), (IDIS
| PTU
| EN
| M0
));
55 MUX_VAL(CP(SDRC_CKE1
), (IDIS
| PTD
| DIS
| M7
));
58 MUX_VAL(CP(GPMC_A1
), (IDIS
| PTU
| EN
| M0
));
59 MUX_VAL(CP(GPMC_A2
), (IDIS
| PTU
| EN
| M0
));
60 MUX_VAL(CP(GPMC_A3
), (IDIS
| PTU
| EN
| M0
));
61 MUX_VAL(CP(GPMC_A4
), (IDIS
| PTU
| EN
| M0
));
62 MUX_VAL(CP(GPMC_A5
), (IDIS
| PTU
| EN
| M0
));
63 MUX_VAL(CP(GPMC_A6
), (IDIS
| PTU
| EN
| M0
));
64 MUX_VAL(CP(GPMC_A7
), (IDIS
| PTU
| EN
| M0
));
65 MUX_VAL(CP(GPMC_A8
), (IDIS
| PTU
| EN
| M0
));
66 MUX_VAL(CP(GPMC_A9
), (IDIS
| PTU
| EN
| M0
));
67 MUX_VAL(CP(GPMC_A10
), (IDIS
| PTU
| EN
| M0
));
68 MUX_VAL(CP(GPMC_D0
), (IEN
| PTU
| EN
| M0
));
69 MUX_VAL(CP(GPMC_D1
), (IEN
| PTU
| EN
| M0
));
70 MUX_VAL(CP(GPMC_D2
), (IEN
| PTU
| EN
| M0
));
71 MUX_VAL(CP(GPMC_D3
), (IEN
| PTU
| EN
| M0
));
72 MUX_VAL(CP(GPMC_D4
), (IEN
| PTU
| EN
| M0
));
73 MUX_VAL(CP(GPMC_D5
), (IEN
| PTU
| EN
| M0
));
74 MUX_VAL(CP(GPMC_D6
), (IEN
| PTU
| EN
| M0
));
75 MUX_VAL(CP(GPMC_D7
), (IEN
| PTU
| EN
| M0
));
76 MUX_VAL(CP(GPMC_D8
), (IEN
| PTU
| EN
| M0
));
77 MUX_VAL(CP(GPMC_D9
), (IEN
| PTU
| EN
| M0
));
78 MUX_VAL(CP(GPMC_D10
), (IEN
| PTU
| EN
| M0
));
79 MUX_VAL(CP(GPMC_D11
), (IEN
| PTU
| EN
| M0
));
80 MUX_VAL(CP(GPMC_D12
), (IEN
| PTU
| EN
| M0
));
81 MUX_VAL(CP(GPMC_D13
), (IEN
| PTU
| EN
| M0
));
82 MUX_VAL(CP(GPMC_D14
), (IEN
| PTU
| EN
| M0
));
83 MUX_VAL(CP(GPMC_D15
), (IEN
| PTU
| EN
| M0
));
84 MUX_VAL(CP(GPMC_NCS0
), (IDIS
| PTU
| EN
| M0
));
86 /* SB-T35 SD/MMC WP GPIO59 */
87 MUX_VAL(CP(GPMC_CLK
), (IEN
| PTU
| EN
| M4
)); /*GPIO_59*/
88 MUX_VAL(CP(GPMC_NWE
), (IDIS
| PTD
| DIS
| M0
));
89 MUX_VAL(CP(GPMC_NOE
), (IDIS
| PTD
| DIS
| M0
));
90 MUX_VAL(CP(GPMC_NADV_ALE
), (IDIS
| PTD
| DIS
| M0
));
91 MUX_VAL(CP(GPMC_NBE0_CLE
), (IDIS
| PTU
| EN
| M0
));
92 /* SB-T35 Audio Enable GPIO61 */
93 MUX_VAL(CP(GPMC_NBE1
), (IDIS
| PTU
| EN
| M4
)); /*GPIO_61*/
94 MUX_VAL(CP(GPMC_NWP
), (IEN
| PTD
| DIS
| M0
));
95 MUX_VAL(CP(GPMC_WAIT0
), (IEN
| PTU
| EN
| M0
));
98 MUX_VAL(CP(UART3_RX_IRRX
), (IEN
| PTD
| DIS
| M0
));
99 MUX_VAL(CP(UART3_TX_IRTX
), (IDIS
| PTD
| DIS
| M0
));
100 /* RTC V3020 nCS GPIO163 */
101 MUX_VAL(CP(UART3_CTS_RCTX
), (IEN
| PTU
| EN
| M4
)); /*GPIO_163*/
103 /* SB-T35 SD/MMC CD GPIO144 */
104 MUX_VAL(CP(UART2_CTS
), (IEN
| PTU
| EN
| M4
)); /*GPIO_144*/
105 /* WIFI nRESET GPIO145 */
106 MUX_VAL(CP(UART2_RTS
), (IEN
| PTD
| EN
| M4
)); /*GPIO_145*/
107 /* USB1 PHY Reset GPIO 146 */
108 MUX_VAL(CP(UART2_TX
), (IEN
| PTD
| EN
| M4
)); /*GPIO_146*/
109 /* USB2 PHY Reset GPIO 147 */
110 MUX_VAL(CP(UART2_RX
), (IEN
| PTD
| EN
| M4
)); /*GPIO_147*/
113 MUX_VAL(CP(MMC1_CLK
), (IDIS
| PTU
| EN
| M0
));
114 MUX_VAL(CP(MMC1_CMD
), (IEN
| PTU
| EN
| M0
));
115 MUX_VAL(CP(MMC1_DAT0
), (IEN
| PTU
| EN
| M0
));
116 MUX_VAL(CP(MMC1_DAT1
), (IEN
| PTU
| EN
| M0
));
117 MUX_VAL(CP(MMC1_DAT2
), (IEN
| PTU
| EN
| M0
));
118 MUX_VAL(CP(MMC1_DAT3
), (IEN
| PTU
| EN
| M0
));
121 MUX_VAL(CP(I2C1_SCL
), (IEN
| PTU
| EN
| M0
));
122 MUX_VAL(CP(I2C1_SDA
), (IEN
| PTU
| EN
| M0
));
123 MUX_VAL(CP(I2C3_SCL
), (IEN
| PTU
| EN
| M0
));
124 MUX_VAL(CP(I2C3_SDA
), (IEN
| PTU
| EN
| M0
));
126 /* SB-T35 USB HUB Reset GPIO98 */
127 MUX_VAL(CP(CCDC_WEN
), (IDIS
| PTU
| EN
| M4
)); /*GPIO_98*/
128 /* CM-T3517 USB HUB Reset GPIO152 */
129 MUX_VAL(CP(MCBSP4_CLKX
), (IDIS
| PTD
| DIS
| M4
)); /*GPIO_152*/
131 /* Green LED GPIO186 */
132 MUX_VAL(CP(SYS_CLKOUT2
), (IDIS
| PTU
| DIS
| M4
)); /*GPIO_186*/
134 /* RTC V3020 CS Enable GPIO160 */
135 MUX_VAL(CP(MCBSP_CLKS
), (IEN
| PTD
| EN
| M4
)); /*GPIO_160*/
138 MUX_VAL(CP(USB0_DRVBUS
), (IEN
| PTD
| EN
| M0
));
140 MUX_VAL(CP(ETK_D0_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB1_DT0*/
141 MUX_VAL(CP(ETK_D1_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB1_DT1*/
142 MUX_VAL(CP(ETK_D2_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB1_DT2*/
143 MUX_VAL(CP(ETK_D7_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB1_DT3*/
144 MUX_VAL(CP(ETK_D4_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB1_DT4*/
145 MUX_VAL(CP(ETK_D5_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB1_DT5*/
146 MUX_VAL(CP(ETK_D6_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB1_DT6*/
147 MUX_VAL(CP(ETK_D3_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB1_DT7*/
148 MUX_VAL(CP(ETK_D8_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB1_DIR*/
149 MUX_VAL(CP(ETK_D9_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB1_NXT*/
150 MUX_VAL(CP(ETK_CTL_ES2
), (IDIS
| PTD
| DIS
| M3
)); /*HSUSB1_CLK*/
151 MUX_VAL(CP(ETK_CLK_ES2
), (IDIS
| PTU
| DIS
| M3
)); /*HSUSB1_STP*/
153 MUX_VAL(CP(ETK_D14_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB2_DT0*/
154 MUX_VAL(CP(ETK_D15_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB2_DT1*/
155 MUX_VAL(CP(MCSPI1_CS3
), (IEN
| PTD
| EN
| M3
)); /*HSUSB2_DT2*/
156 MUX_VAL(CP(MCSPI2_CS1
), (IEN
| PTD
| EN
| M3
)); /*HSUSB2_DT3*/
157 MUX_VAL(CP(MCSPI2_SIMO
), (IEN
| PTD
| EN
| M3
)); /*HSUSB2_DT4*/
158 MUX_VAL(CP(MCSPI2_SOMI
), (IEN
| PTD
| EN
| M3
)); /*HSUSB2_DT5*/
159 MUX_VAL(CP(MCSPI2_CS0
), (IEN
| PTD
| EN
| M3
)); /*HSUSB2_DT6*/
160 MUX_VAL(CP(MCSPI2_CLK
), (IEN
| PTD
| EN
| M3
)); /*HSUSB2_DT7*/
161 MUX_VAL(CP(ETK_D12_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB2_DIR*/
162 MUX_VAL(CP(ETK_D13_ES2
), (IEN
| PTD
| EN
| M3
)); /*HSUSB2_NXT*/
163 MUX_VAL(CP(ETK_D10_ES2
), (IDIS
| PTD
| DIS
| M3
)); /*HSUSB2_CLK*/
164 MUX_VAL(CP(ETK_D11_ES2
), (IDIS
| PTU
| DIS
| M3
)); /*HSUSB2_STP*/
167 MUX_VAL(CP(SYS_BOOT0
), (IEN
| PTU
| DIS
| M4
)); /*GPIO_2*/
168 MUX_VAL(CP(SYS_BOOT1
), (IEN
| PTU
| DIS
| M4
)); /*GPIO_3*/
169 MUX_VAL(CP(SYS_BOOT2
), (IEN
| PTU
| DIS
| M4
)); /*GPIO_4*/
170 MUX_VAL(CP(SYS_BOOT3
), (IEN
| PTU
| DIS
| M4
)); /*GPIO_5*/
171 MUX_VAL(CP(SYS_BOOT4
), (IEN
| PTU
| DIS
| M4
)); /*GPIO_6*/
172 MUX_VAL(CP(SYS_BOOT5
), (IEN
| PTU
| DIS
| M4
)); /*GPIO_7*/