board/compulab/cm_t43/cm_t43.c

   1 /*
   2  * Copyright (C) 2015 Compulab, Ltd.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <miiphy.h>
  10 #include <cpsw.h>
  11 #include <asm/gpio.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/emif.h>
  14 #include <power/pmic.h>
  15 #include <power/tps65218.h>
  16 #include "board.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  21
  22 /* setup board specific PMIC */
  23 int power_init_board(void)
  24 {
  25         struct pmic *p;
  26         uchar tps_status = 0;
  27
  28         power_tps65218_init(I2C_PMIC);
  29         p = pmic_get("TPS65218_PMIC");
  30         if (p && !pmic_probe(p)) {
  31                 puts("PMIC:  TPS65218\n");
  32                 /* We don't care if fseal is locked, but we do need it set */
  33                 tps65218_lock_fseal();
  34                 tps65218_reg_read(TPS65218_STATUS, &tps_status);
  35                 if (!(tps_status & TPS65218_FSEAL))
  36                         printf("WARNING: RTC not backed by battery!\n");
  37         }
  38
  39         return 0;
  40 }
  41
  42 int board_init(void)
  43 {
  44         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  45         gpmc_init();
  46         set_i2c_pin_mux();
  47         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  48         i2c_probe(TPS65218_CHIP_PM);
  49
  50         return 0;
  51 }
  52
  53 #ifdef CONFIG_DRIVER_TI_CPSW
  54
  55 static void cpsw_control(int enabled)
  56 {
  57         return;
  58 }
  59
  60 static struct cpsw_slave_data cpsw_slaves[] = {
  61         {
  62                 .slave_reg_ofs  = 0x208,
  63                 .sliver_reg_ofs = 0xd80,
  64                 .phy_addr       = 0,
  65                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
  66         },
  67         {
  68                 .slave_reg_ofs  = 0x308,
  69                 .sliver_reg_ofs = 0xdc0,
  70                 .phy_addr       = 1,
  71                 .phy_if         = PHY_INTERFACE_MODE_RGMII,
  72         },
  73 };
  74
  75 static struct cpsw_platform_data cpsw_data = {
  76         .mdio_base              = CPSW_MDIO_BASE,
  77         .cpsw_base              = CPSW_BASE,
  78         .mdio_div               = 0xff,
  79         .channels               = 8,
  80         .cpdma_reg_ofs          = 0x800,
  81         .slaves                 = 2,
  82         .slave_data             = cpsw_slaves,
  83         .ale_reg_ofs            = 0xd00,
  84         .ale_entries            = 1024,
  85         .host_port_reg_ofs      = 0x108,
  86         .hw_stats_reg_ofs       = 0x900,
  87         .bd_ram_ofs             = 0x2000,
  88         .mac_control            = (1 << 5),
  89         .control                = cpsw_control,
  90         .host_port_num          = 0,
  91         .version                = CPSW_CTRL_VERSION_2,
  92 };
  93
  94 #define GPIO_PHY1_RST           170
  95 #define GPIO_PHY2_RST           168
  96
  97 int board_phy_config(struct phy_device *phydev)
  98 {
  99         unsigned short val;
 100
 101         /* introduce tx clock delay */
 102         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 103         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 104         val |= 0x0100;
 105         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 106
 107         if (phydev->drv->config)
 108                 return phydev->drv->config(phydev);
 109
 110         return 0;
 111 }
 112
 113 static void board_phy_init(void)
 114 {
 115         set_mdio_pin_mux();
 116         writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
 117         writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
 118         writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
 119
 120         /* For revision A */
 121         writel(0x2000009, 0x44df2e6c);
 122         writel(0x38a, 0x44df2e70);
 123
 124         mdelay(10);
 125
 126         gpio_request(GPIO_PHY1_RST, "phy1_rst");
 127         gpio_request(GPIO_PHY2_RST, "phy2_rst");
 128         gpio_direction_output(GPIO_PHY1_RST, 0);
 129         gpio_direction_output(GPIO_PHY2_RST, 0);
 130         mdelay(2);
 131
 132         gpio_set_value(GPIO_PHY1_RST, 1);
 133         gpio_set_value(GPIO_PHY2_RST, 1);
 134         mdelay(2);
 135 }
 136
 137 int board_eth_init(bd_t *bis)
 138 {
 139         int rv;
 140
 141         set_rgmii_pin_mux();
 142         writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
 143         board_phy_init();
 144
 145         rv = cpsw_register(&cpsw_data);
 146         if (rv < 0)
 147                 printf("Error %d registering CPSW switch\n", rv);
 148
 149         return rv;
 150 }
 151 #endif