2 * Copyright (C) 2015 Compulab, Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/sys_proto.h>
14 #include <power/pmic.h>
15 #include <power/tps65218.h>
18 #include <asm/omap_common.h>
20 DECLARE_GLOBAL_DATA_PTR
;
22 static struct ctrl_dev
*cdev
= (struct ctrl_dev
*)CTRL_DEVICE_BASE
;
24 /* setup board specific PMIC */
25 int power_init_board(void)
30 power_tps65218_init(I2C_PMIC
);
31 p
= pmic_get("TPS65218_PMIC");
32 if (p
&& !pmic_probe(p
)) {
33 puts("PMIC: TPS65218\n");
34 /* We don't care if fseal is locked, but we do need it set */
35 tps65218_lock_fseal();
36 tps65218_reg_read(TPS65218_STATUS
, &tps_status
);
37 if (!(tps_status
& TPS65218_FSEAL
))
38 printf("WARNING: RTC not backed by battery!\n");
46 gd
->bd
->bi_boot_params
= CONFIG_SYS_SDRAM_BASE
+ 0x100;
49 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED
, CONFIG_SYS_OMAP24_I2C_SLAVE
);
50 i2c_probe(TPS65218_CHIP_PM
);
55 int board_usb_init(int index
, enum usb_init_type init
)
57 enable_usb_clocks(index
);
61 int board_usb_cleanup(int index
, enum usb_init_type init
)
63 disable_usb_clocks(index
);
67 #ifdef CONFIG_DRIVER_TI_CPSW
69 static void cpsw_control(int enabled
)
74 static struct cpsw_slave_data cpsw_slaves
[] = {
76 .slave_reg_ofs
= 0x208,
77 .sliver_reg_ofs
= 0xd80,
79 .phy_if
= PHY_INTERFACE_MODE_RGMII
,
82 .slave_reg_ofs
= 0x308,
83 .sliver_reg_ofs
= 0xdc0,
85 .phy_if
= PHY_INTERFACE_MODE_RGMII
,
89 static struct cpsw_platform_data cpsw_data
= {
90 .mdio_base
= CPSW_MDIO_BASE
,
91 .cpsw_base
= CPSW_BASE
,
94 .cpdma_reg_ofs
= 0x800,
96 .slave_data
= cpsw_slaves
,
99 .host_port_reg_ofs
= 0x108,
100 .hw_stats_reg_ofs
= 0x900,
101 .bd_ram_ofs
= 0x2000,
102 .mac_control
= (1 << 5),
103 .control
= cpsw_control
,
105 .version
= CPSW_CTRL_VERSION_2
,
108 #define GPIO_PHY1_RST 170
109 #define GPIO_PHY2_RST 168
111 int board_phy_config(struct phy_device
*phydev
)
115 /* introduce tx clock delay */
116 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1d, 0x5);
117 val
= phy_read(phydev
, MDIO_DEVAD_NONE
, 0x1e);
119 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, val
);
121 if (phydev
->drv
->config
)
122 return phydev
->drv
->config(phydev
);
127 static void board_phy_init(void)
130 writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
131 writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
132 writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
135 writel(0x2000009, 0x44df2e6c);
136 writel(0x38a, 0x44df2e70);
140 gpio_request(GPIO_PHY1_RST
, "phy1_rst");
141 gpio_request(GPIO_PHY2_RST
, "phy2_rst");
142 gpio_direction_output(GPIO_PHY1_RST
, 0);
143 gpio_direction_output(GPIO_PHY2_RST
, 0);
146 gpio_set_value(GPIO_PHY1_RST
, 1);
147 gpio_set_value(GPIO_PHY2_RST
, 1);
151 int board_eth_init(bd_t
*bis
)
156 writel(RGMII_MODE_ENABLE
| RGMII_INT_DELAY
, &cdev
->miisel
);
159 rv
= cpsw_register(&cpsw_data
);
161 printf("Error %d registering CPSW switch\n", rv
);