board/csb272/csb272.c

   1 /*
   2  * (C) Copyright 2004
   3  * Tolunay Orkun, Nextio Inc., torkun@nextio.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <i2c.h>
  27 #include <miiphy.h>
  28 #include <asm/ppc4xx-emac.h>
  29
  30 void sdram_init(void);
  31
  32 /*
  33  * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
  34  *
  35  * CLKA output => Epson LCD Controller
  36  * CLKB output => Not Connected
  37  * CLKC output => Ethernet
  38  * CLKD output => UART external clock
  39  *
  40  * Note: these values are obtained from device after init by micromonitor
  41 */
  42 uchar pll_fs6377_regs[16] = {
  43         0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
  44         0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
  45
  46 /*
  47  * pll_init: Initialize AMIS IC FS6377-01 PLL
  48  *
  49  * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
  50  *
  51  */
  52 int pll_init(void)
  53 {
  54         i2c_set_bus_num(0);
  55
  56         return  i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1,
  57                 (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
  58 }
  59
  60 /*
  61  * board_early_init_f: do early board initialization
  62  *
  63  */
  64 int board_early_init_f(void)
  65 {
  66         /* initialize PLL so UART, LCD, Ethernet clocked at correctly */
  67         (void) get_clocks();
  68         pll_init();
  69
  70    /*-------------------------------------------------------------------------+
  71    | Interrupt controller setup for the Walnut board.
  72    | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
  73    |       IRQ 16    405GP internally generated; active low; level sensitive
  74    |       IRQ 17-24 RESERVED
  75    |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
  76    |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
  77    |       IRQ 27 (EXT IRQ 2) Not Used
  78    |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  79    |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  80    |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  81    |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  82    | Note for Walnut board:
  83    |       An interrupt taken for the FPGA (IRQ 25) indicates that either
  84    |       the Mouse, Keyboard, IRDA, or External Expansion caused the
  85    |       interrupt. The FPGA must be read to determine which device
  86    |       caused the interrupt. The default setting of the FPGA clears
  87    |
  88    +-------------------------------------------------------------------------*/
  89
  90         mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
  91         mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
  92         mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
  93         mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
  94         mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
  95         mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
  96         mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
  97
  98         mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
  99
 100         return 0; /* success */
 101 }
 102
 103 /*
 104  * checkboard: identify/verify the board we are running
 105  *
 106  * Remark: we just assume it is correct board here!
 107  *
 108  */
 109 int checkboard(void)
 110 {
 111         printf("BOARD: Cogent CSB272\n");
 112
 113         return 0; /* success */
 114 }
 115
 116 /*
 117  * initram: Determine the size of mounted DRAM
 118  *
 119  * Size is determined by reading SDRAM configuration registers as
 120  * configured by initialization code
 121  *
 122  */
 123 phys_size_t initdram (int board_type)
 124 {
 125         ulong tot_size;
 126         ulong bank_size;
 127         ulong tmp;
 128
 129         /*
 130          * ToDo: Move the asm init routine sdram_init() to this C file,
 131          * or even better use some common ppc4xx code available
 132          * in arch/powerpc/cpu/ppc4xx
 133          */
 134         sdram_init();
 135
 136         tot_size = 0;
 137
 138         mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
 139         tmp = mfdcr (SDRAM0_CFGDATA);
 140         if (tmp & 0x00000001) {
 141                 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 142                 tot_size += bank_size;
 143         }
 144
 145         mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
 146         tmp = mfdcr (SDRAM0_CFGDATA);
 147         if (tmp & 0x00000001) {
 148                 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 149                 tot_size += bank_size;
 150         }
 151
 152         mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
 153         tmp = mfdcr (SDRAM0_CFGDATA);
 154         if (tmp & 0x00000001) {
 155                 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 156                 tot_size += bank_size;
 157         }
 158
 159         mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
 160         tmp = mfdcr (SDRAM0_CFGDATA);
 161         if (tmp & 0x00000001) {
 162                 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 163                 tot_size += bank_size;
 164         }
 165
 166         return tot_size;
 167 }
 168
 169 /*
 170  * last_stage_init: final configurations (such as PHY etc)
 171  *
 172  */
 173 int last_stage_init(void)
 174 {
 175         /* initialize the PHY */
 176         miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
 177
 178         /* AUTO neg */
 179         miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
 180                         BMCR_ANENABLE | BMCR_ANRESTART);
 181
 182         /* LEDs     */
 183         miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
 184
 185
 186         return 0; /* success */
 187 }