board/davedenx/qong/qong.c

   1 /*
   2  *
   3  * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <netdev.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/imx-regs.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <asm/io.h>
  30 #include <nand.h>
  31 #include <power/pmic.h>
  32 #include <fsl_pmic.h>
  33 #include <asm/gpio.h>
  34 #include "qong_fpga.h"
  35 #include <watchdog.h>
  36 #include <errno.h>
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 int dram_init(void)
  41 {
  42         /* dram_init must store complete ramsize in gd->ram_size */
  43         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  44                                 PHYS_SDRAM_1_SIZE);
  45         return 0;
  46 }
  47
  48 static void qong_fpga_reset(void)
  49 {
  50         gpio_set_value(QONG_FPGA_RST_PIN, 0);
  51         udelay(30);
  52         gpio_set_value(QONG_FPGA_RST_PIN, 1);
  53
  54         udelay(300);
  55 }
  56
  57 int board_early_init_f(void)
  58 {
  59 #ifdef CONFIG_QONG_FPGA
  60         /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
  61         static const struct mxc_weimcs cs1 = {
  62                 /*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
  63                 CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  0, 10, 0,  0,  1),
  64                 /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
  65                 CSCR_L(2,  0,   0,   4,  0,  0,  5,  0,  0,  0,   0,   1),
  66                 /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
  67                 CSCR_A(0,   4,  0,  2,  0,  0,  3,  0,  0,  0,  0,  0,   0,  0)
  68         };
  69
  70         mxc_setup_weimcs(1, &cs1);
  71
  72         /* setup pins for FPGA */
  73         mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
  74         mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
  75         mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
  76         mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
  77         mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
  78
  79         /* FPGA reset  Pin */
  80         /* rstn = 0 */
  81         gpio_direction_output(QONG_FPGA_RST_PIN, 0);
  82
  83         /* set interrupt pin as input */
  84         gpio_direction_input(QONG_FPGA_IRQ_PIN);
  85
  86         /* FPGA JTAG Interface */
  87         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
  88         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
  89         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
  90         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
  91         gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
  92         gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
  93         gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
  94         gpio_direction_input(QONG_FPGA_TDO_PIN);
  95 #endif
  96
  97         /* setup pins for UART1 */
  98         mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
  99         mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
 100         mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
 101         mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 102
 103         /* setup pins for SPI (pmic) */
 104         mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
 105         mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
 106         mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
 107         mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
 108         mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
 109
 110         /* Setup pins for USB2 Host */
 111         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
 112         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
 113         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
 114         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
 115         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
 116         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
 117
 118 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
 119                         PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
 120
 121         mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
 122         mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
 123         mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
 124         mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
 125         mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
 126         mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
 127         mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);       /* USBH2_DATA2 */
 128         mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);       /* USBH2_DATA3 */
 129         mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);        /* USBH2_DATA4 */
 130         mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);        /* USBH2_DATA5 */
 131         mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);       /* USBH2_DATA6 */
 132         mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);       /* USBH2_DATA7 */
 133
 134         mx31_set_gpr(MUX_PGP_UH2, 1);
 135
 136         return 0;
 137
 138 }
 139
 140 int board_init(void)
 141 {
 142         /* Chip selects */
 143         /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
 144         /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
 145         static const struct mxc_weimcs cs0 = {
 146                 /*     sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
 147                 CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 21, 0,  0,  6),
 148                 /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
 149                 CSCR_L(0,  1,   3,   3,  1,  1,  5,  1,  0,  0,   0,  1),
 150                 /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
 151                 CSCR_A(0,   1,  2,  2,  0,  0,  2,  0,  0,  0,  0,  0,   0,  0)
 152         };
 153
 154         mxc_setup_weimcs(0, &cs0);
 155
 156         /* board id for linux */
 157         gd->bd->bi_arch_number = MACH_TYPE_QONG;
 158         gd->bd->bi_boot_params = (0x80000100);  /* adress of boot parameters */
 159
 160         qong_fpga_init();
 161
 162         return 0;
 163 }
 164
 165 int board_late_init(void)
 166 {
 167         u32 val;
 168         struct pmic *p;
 169         int ret;
 170
 171         ret = pmic_init(I2C_PMIC);
 172         if (ret)
 173                 return ret;
 174
 175         p = pmic_get("FSL_PMIC");
 176         if (!p)
 177                 return -ENODEV;
 178         /* Enable RTC battery */
 179         pmic_reg_read(p, REG_POWER_CTL0, &val);
 180         pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
 181         pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
 182
 183 #ifdef CONFIG_HW_WATCHDOG
 184         hw_watchdog_init();
 185 #endif
 186
 187         return 0;
 188 }
 189
 190 int checkboard(void)
 191 {
 192         printf("Board: DAVE/DENX Qong\n");
 193         return 0;
 194 }
 195
 196 int misc_init_r(void)
 197 {
 198 #ifdef CONFIG_QONG_FPGA
 199         u32 tmp;
 200
 201         tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
 202         printf("FPGA:  ");
 203         printf("version register = %u.%u.%u\n",
 204                 (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
 205 #endif
 206         return 0;
 207 }
 208
 209 int board_eth_init(bd_t *bis)
 210 {
 211 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
 212         return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
 213 #else
 214         return 0;
 215 #endif
 216 }
 217
 218 #if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
 219 static void board_nand_setup(void)
 220 {
 221         /* CS3: NAND 8-bit */
 222         static const struct mxc_weimcs cs3 = {
 223                 /*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
 224                 CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  1, 15, 0,  0,  0),
 225                 /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
 226                 CSCR_L(2,  0,   0,   1,  3,  1,  3,  3,  0,  0,   0,   1),
 227                 /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
 228                 CSCR_A(0,   0,  0,  2,  0,  0,  2,  0,  0,  0,  0,  0,  0,   0)
 229         };
 230
 231         mxc_setup_weimcs(3, &cs3);
 232
 233         mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
 234
 235         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
 236         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
 237         mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
 238
 239         /* Make sure to reset the fpga else you cannot access NAND */
 240         qong_fpga_reset();
 241
 242         /* Enable NAND flash */
 243         gpio_set_value(15, 1);
 244         gpio_set_value(14, 1);
 245         gpio_direction_output(15, 0);
 246         gpio_direction_input(16);
 247         gpio_direction_input(14);
 248
 249 }
 250
 251 int qong_nand_rdy(void *chip)
 252 {
 253         udelay(1);
 254         return gpio_get_value(16);
 255 }
 256
 257 void qong_nand_select_chip(struct mtd_info *mtd, int chip)
 258 {
 259         if (chip >= 0)
 260                 gpio_set_value(15, 0);
 261         else
 262                 gpio_set_value(15, 1);
 263
 264 }
 265
 266 void qong_nand_plat_init(void *chip)
 267 {
 268         struct nand_chip *nand = (struct nand_chip *)chip;
 269         nand->chip_delay = 20;
 270         nand->select_chip = qong_nand_select_chip;
 271         nand->options &= ~NAND_BUSWIDTH_16;
 272         board_nand_setup();
 273 }
 274
 275 #endif