board/davinci/dm355leopard/dm355leopard.c

   1 /*
   2  * Copyright (C) 2009 Texas Instruments Incorporated
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <nand.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/gpio.h>
  12 #include <asm/arch/nand_defs.h>
  13 #include <asm/arch/davinci_misc.h>
  14 #include <net.h>
  15 #include <netdev.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 int board_init(void)
  20 {
  21         struct davinci_gpio *gpio01_base =
  22                         (struct davinci_gpio *)DAVINCI_GPIO_BANK01;
  23         struct davinci_gpio *gpio23_base =
  24                         (struct davinci_gpio *)DAVINCI_GPIO_BANK23;
  25         struct davinci_gpio *gpio67_base =
  26                         (struct davinci_gpio *)DAVINCI_GPIO_BANK67;
  27
  28         gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
  29         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  30
  31         /* GIO 9 & 10 are used for IO */
  32         writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
  33
  34         /* Interrupt set GIO 9 */
  35         writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
  36
  37         /* set GIO 9 input */
  38         writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
  39
  40         /* Both edge trigger GIO 9 */
  41         writel((readl(&gpio01_base->set_rising) | (1 << 9)),
  42                                                 &gpio01_base->set_rising);
  43         writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
  44
  45         /* output low */
  46         writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
  47                                                 &gpio01_base->set_data);
  48
  49         /* set GIO 10 output */
  50         writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
  51
  52         /* output high */
  53         writel((readl(&gpio01_base->set_data) | (1 << 10)),
  54                                                 &gpio01_base->set_data);
  55
  56         /* set GIO 32 output */
  57         writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
  58
  59         /* output High */
  60         writel((readl(&gpio23_base->set_data) | (1 << 0)),
  61                                                 &gpio23_base->set_data);
  62
  63         /* Enable UART1 MUX Lines */
  64         writel((readl(PINMUX0) & ~3), PINMUX0);
  65         writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
  66         writel((readl(&gpio67_base->set_data) | (1 << 6)),
  67                                                 &gpio67_base->set_data);
  68
  69         return 0;
  70 }
  71
  72 #ifdef CONFIG_DRIVER_DM9000
  73 int board_eth_init(bd_t *bis)
  74 {
  75         return dm9000_initialize(bis);
  76 }
  77 #endif
  78
  79 #ifdef CONFIG_NAND_DAVINCI
  80 int board_nand_init(struct nand_chip *nand)
  81 {
  82         davinci_nand_init(nand);
  83
  84         return 0;
  85 }
  86 #endif