board/denx/m53evk/m53evk.c

   1 /*
   2  * DENX M53 module
   3  *
   4  * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <asm/arch/crm_regs.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/iomux-mx53.h>
  16 #include <asm/imx-common/mx5_video.h>
  17 #include <asm/arch/spl.h>
  18 #include <asm/errno.h>
  19 #include <netdev.h>
  20 #include <i2c.h>
  21 #include <mmc.h>
  22 #include <spl.h>
  23 #include <fsl_esdhc.h>
  24 #include <asm/gpio.h>
  25 #include <usb/ehci-fsl.h>
  26 #include <linux/fb.h>
  27 #include <ipu_pixfmt.h>
  28
  29 /* Special MXCFB sync flags are here. */
  30 #include "../drivers/video/mxcfb.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 int dram_init(void)
  35 {
  36         u32 size1, size2;
  37
  38         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  39         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  40
  41         gd->ram_size = size1 + size2;
  42
  43         return 0;
  44 }
  45 void dram_init_banksize(void)
  46 {
  47         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  48         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  49
  50         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  51         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  52 }
  53
  54 static void setup_iomux_uart(void)
  55 {
  56         static const iomux_v3_cfg_t uart_pads[] = {
  57                 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  58                 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  59         };
  60
  61         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  62 }
  63
  64 #ifdef CONFIG_USB_EHCI_MX5
  65 int board_ehci_hcd_init(int port)
  66 {
  67         if (port == 0) {
  68                 /* USB OTG PWRON */
  69                 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
  70                                         PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
  71                 gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
  72
  73                 /* USB OTG Over Current */
  74                 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
  75         } else if (port == 1) {
  76                 /* USB Host PWRON */
  77                 imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
  78                                         PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
  79                 gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
  80
  81                 /* USB Host Over Current */
  82                 imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
  83         }
  84
  85         return 0;
  86 }
  87 #endif
  88
  89 static void setup_iomux_fec(void)
  90 {
  91         static const iomux_v3_cfg_t fec_pads[] = {
  92                 /* MDIO pads */
  93                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  94                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  95                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  96
  97                 /* FEC 0 pads */
  98                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  99                                 PAD_CTL_HYS | PAD_CTL_PKE),
 100                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
 101                                 PAD_CTL_HYS | PAD_CTL_PKE),
 102                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 103                                 PAD_CTL_HYS | PAD_CTL_PKE),
 104                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
 105                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 106                                 PAD_CTL_HYS | PAD_CTL_PKE),
 107                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 108                                 PAD_CTL_HYS | PAD_CTL_PKE),
 109                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 110                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 111
 112                 /* FEC 1 pads */
 113                 NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
 114                                 PAD_CTL_HYS | PAD_CTL_PKE),
 115                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
 116                                 PAD_CTL_HYS | PAD_CTL_PKE),
 117                 NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
 118                                 PAD_CTL_HYS | PAD_CTL_PKE),
 119                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
 120                                 PAD_CTL_HYS | PAD_CTL_PKE),
 121                 NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
 122                                 PAD_CTL_HYS | PAD_CTL_PKE),
 123                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
 124                 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
 125                                 PAD_CTL_HYS | PAD_CTL_PKE),
 126                 NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
 127         };
 128
 129         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 130 }
 131
 132 #ifdef CONFIG_FSL_ESDHC
 133 struct fsl_esdhc_cfg esdhc_cfg = {
 134         MMC_SDHC1_BASE_ADDR,
 135 };
 136
 137 int board_mmc_getcd(struct mmc *mmc)
 138 {
 139         imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
 140         gpio_direction_input(IMX_GPIO_NR(1, 1));
 141
 142         return !gpio_get_value(IMX_GPIO_NR(1, 1));
 143 }
 144
 145 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 146                                  PAD_CTL_PUS_100K_UP)
 147 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 148                                  PAD_CTL_DSE_HIGH)
 149
 150 int board_mmc_init(bd_t *bis)
 151 {
 152         static const iomux_v3_cfg_t sd1_pads[] = {
 153                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 154                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 155                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 156                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 157                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 158                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 159                 MX53_PAD_EIM_DA13__GPIO3_13,
 160
 161                 MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
 162         };
 163
 164         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 165
 166         imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
 167
 168         /* GPIO 2_31 is SD power */
 169         gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
 170
 171         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 172 }
 173 #endif
 174
 175 #ifdef CONFIG_VIDEO
 176 static struct fb_videomode const ampire_wvga = {
 177         .name           = "Ampire",
 178         .refresh        = 60,
 179         .xres           = 800,
 180         .yres           = 480,
 181         .pixclock       = 29851, /* picosecond (33.5 MHz) */
 182         .left_margin    = 89,
 183         .right_margin   = 164,
 184         .upper_margin   = 23,
 185         .lower_margin   = 10,
 186         .hsync_len      = 10,
 187         .vsync_len      = 10,
 188         .sync           = FB_SYNC_CLK_LAT_FALL,
 189 };
 190
 191 int board_video_skip(void)
 192 {
 193         int ret;
 194         ret = ipuv3_fb_init(&ampire_wvga, 1, IPU_PIX_FMT_RGB666);
 195         if (ret)
 196                 printf("Ampire LCD cannot be configured: %d\n", ret);
 197         return ret;
 198 }
 199 #endif
 200
 201 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 202                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 203
 204 static void setup_iomux_i2c(void)
 205 {
 206         static const iomux_v3_cfg_t i2c_pads[] = {
 207                 NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
 208                 NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
 209         };
 210
 211         imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
 212 }
 213
 214 static void setup_iomux_video(void)
 215 {
 216         static const iomux_v3_cfg_t lcd_pads[] = {
 217                 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
 218                 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
 219                 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
 220                 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
 221                 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
 222                 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
 223                 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
 224                 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
 225                 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
 226                 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
 227                 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
 228                 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
 229                 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
 230                 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
 231                 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
 232                 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
 233                 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
 234                 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
 235                 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
 236                 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
 237                 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
 238                 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
 239                 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
 240                 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
 241                 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
 242                 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
 243                 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
 244                 MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
 245                 MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
 246                 MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
 247                 MX53_PAD_EIM_A25__IPU_DI1_PIN12,
 248                 MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
 249         };
 250
 251         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 252 }
 253
 254 static void setup_iomux_nand(void)
 255 {
 256         static const iomux_v3_cfg_t nand_pads[] = {
 257                 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
 258                                 PAD_CTL_DSE_HIGH),
 259                 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
 260                                 PAD_CTL_DSE_HIGH),
 261                 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
 262                                 PAD_CTL_DSE_HIGH),
 263                 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
 264                                 PAD_CTL_DSE_HIGH),
 265                 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
 266                                 PAD_CTL_PUS_100K_UP),
 267                 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
 268                                 PAD_CTL_PUS_100K_UP),
 269                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
 270                                 PAD_CTL_DSE_HIGH),
 271                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
 272                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 273                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
 274                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 275                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
 276                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 277                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
 278                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 279                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
 280                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 281                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
 282                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 283                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
 284                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 285                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
 286                                 PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
 287         };
 288
 289         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
 290 }
 291
 292 static void m53_set_clock(void)
 293 {
 294         int ret;
 295         const uint32_t ref_clk = MXC_HCLK;
 296         const uint32_t dramclk = 400;
 297         uint32_t cpuclk;
 298
 299         imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
 300                                             PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
 301         gpio_direction_input(IMX_GPIO_NR(4, 0));
 302
 303         /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
 304         cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
 305
 306         ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
 307         if (ret)
 308                 printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
 309
 310         ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
 311         if (ret) {
 312                 printf("CPU:   Switch peripheral clock to %dMHz failed\n",
 313                         dramclk);
 314         }
 315
 316         ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
 317         if (ret)
 318                 printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
 319 }
 320
 321 static void m53_set_nand(void)
 322 {
 323         u32 i;
 324
 325         /* NAND flash is muxed on ATA pins */
 326         setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
 327
 328         /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
 329         for (i = 0x4; i < 0x94; i += 0x18) {
 330                 clrbits_le32(WEIM_BASE_ADDR + i,
 331                              WEIM_GCR2_MUX16_BYP_GRANT_MASK);
 332         }
 333
 334         mxc_set_clock(0, 33, MXC_NFC_CLK);
 335         enable_nfc_clk(1);
 336 }
 337
 338 int board_early_init_f(void)
 339 {
 340         setup_iomux_uart();
 341         setup_iomux_fec();
 342         setup_iomux_i2c();
 343         setup_iomux_nand();
 344         setup_iomux_video();
 345
 346         m53_set_clock();
 347
 348         mxc_set_sata_internal_clock();
 349
 350         /* NAND clock @ 33MHz */
 351         m53_set_nand();
 352
 353         return 0;
 354 }
 355
 356 int board_init(void)
 357 {
 358         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 359
 360         return 0;
 361 }
 362
 363 int checkboard(void)
 364 {
 365         puts("Board: DENX M53EVK\n");
 366
 367         return 0;
 368 }
 369
 370 /*
 371  * NAND SPL
 372  */
 373 #ifdef CONFIG_SPL_BUILD
 374 void spl_board_init(void)
 375 {
 376         setup_iomux_nand();
 377         m53_set_clock();
 378         m53_set_nand();
 379 }
 380
 381 u32 spl_boot_device(void)
 382 {
 383         return BOOT_DEVICE_NAND;
 384 }
 385 #endif