board/digsy_mtc/digsy_mtc.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * (C) Copyright 2005-2009
   9  * Modified for InterControl digsyMTC MPC5200 board by
  10  * Frank Bodammer, GCD Hard- & Software GmbH,
  11  *                 frank.bodammer@gcd-solutions.de
  12  *
  13  * (C) Copyright 2009
  14  * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #include <common.h>
  36 #include <mpc5xxx.h>
  37 #include <net.h>
  38 #include <pci.h>
  39 #include <asm/processor.h>
  40 #include <asm/io.h>
  41 #include "eeprom.h"
  42 #if defined(CONFIG_DIGSY_REV5)
  43 #include "is45s16800a2.h"
  44 #include <mtd/cfi_flash.h>
  45 #include <flash.h>
  46 #else
  47 #include "is42s16800a-7t.h"
  48 #endif
  49 #include <libfdt.h>
  50 #include <fdt_support.h>
  51 #include <i2c.h>
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 extern int usb_cpu_init(void);
  56
  57 #if defined(CONFIG_DIGSY_REV5)
  58 /*
  59  * The M29W128GH needs a specail reset command function,
  60  * details see the doc/README.cfi file
  61  */
  62 void flash_cmd_reset(flash_info_t *info)
  63 {
  64         flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
  65 }
  66 #endif
  67
  68 #ifndef CONFIG_SYS_RAMBOOT
  69 static void sdram_start(int hi_addr)
  70 {
  71         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  72         long control = SDRAM_CONTROL | hi_addr_bit;
  73
  74         /* unlock mode register */
  75         out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
  76
  77         /* precharge all banks */
  78         out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
  79
  80         /* auto refresh */
  81         out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
  82
  83         /* set mode register */
  84         out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
  85
  86         /* normal operation */
  87         out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
  88 }
  89 #endif
  90
  91 /*
  92  * ATTENTION: Although partially referenced initdram does NOT make real use
  93  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  94  *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  95  */
  96
  97 phys_size_t initdram(int board_type)
  98 {
  99         ulong dramsize = 0;
 100         ulong dramsize2 = 0;
 101         uint svr, pvr;
 102 #ifndef CONFIG_SYS_RAMBOOT
 103         ulong test1, test2;
 104
 105         /* setup SDRAM chip selects */
 106         out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
 107         out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
 108
 109         /* setup config registers */
 110         out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
 111         out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
 112
 113         /* find RAM size using SDRAM CS0 only */
 114         sdram_start(0);
 115         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
 116         sdram_start(1);
 117         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
 118         if (test1 > test2) {
 119                 sdram_start(0);
 120                 dramsize = test1;
 121         } else {
 122                 dramsize = test2;
 123         }
 124
 125         /* memory smaller than 1MB is impossible */
 126         if (dramsize < (1 << 20))
 127                 dramsize = 0;
 128
 129         /* set SDRAM CS0 size according to the amount of RAM found */
 130         if (dramsize > 0) {
 131                 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
 132                         (0x13 + __builtin_ffs(dramsize >> 20) - 1));
 133         } else {
 134                 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
 135         }
 136
 137         /* let SDRAM CS1 start right after CS0 */
 138         out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
 139
 140         /* find RAM size using SDRAM CS1 only */
 141         test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
 142                         0x08000000);
 143                 dramsize2 = test1;
 144
 145         /* memory smaller than 1MB is impossible */
 146         if (dramsize2 < (1 << 20))
 147                 dramsize2 = 0;
 148
 149         /* set SDRAM CS1 size according to the amount of RAM found */
 150         if (dramsize2 > 0) {
 151                 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
 152                         (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
 153         } else {
 154                 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
 155         }
 156
 157 #else /* CONFIG_SYS_RAMBOOT */
 158
 159         /* retrieve size of memory connected to SDRAM CS0 */
 160         dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
 161         if (dramsize >= 0x13)
 162                 dramsize = (1 << (dramsize - 0x13)) << 20;
 163         else
 164                 dramsize = 0;
 165
 166         /* retrieve size of memory connected to SDRAM CS1 */
 167         dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
 168         if (dramsize2 >= 0x13)
 169                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 170         else
 171                 dramsize2 = 0;
 172
 173 #endif /* CONFIG_SYS_RAMBOOT */
 174
 175         /*
 176          * On MPC5200B we need to set the special configuration delay in the
 177          * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 178          * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 179          *
 180          * "The SDelay should be written to a value of 0x00000004. It is
 181          * required to account for changes caused by normal wafer processing
 182          * parameters."
 183          */
 184         svr = get_svr();
 185         pvr = get_pvr();
 186         if ((SVR_MJREV(svr) >= 2) &&
 187             (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
 188                 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
 189
 190         return dramsize + dramsize2;
 191 }
 192
 193 int checkboard(void)
 194 {
 195         char buf[64];
 196         int i = getenv_f("serial#", buf, sizeof(buf));
 197
 198         puts ("Board: InterControl digsyMTC");
 199 #if defined(CONFIG_DIGSY_REV5)
 200         puts (" rev5");
 201 #endif
 202         if (i > 0) {
 203                 puts(", ");
 204                 puts(buf);
 205         }
 206         putc('\n');
 207
 208         return 0;
 209 }
 210
 211 #if defined(CONFIG_VIDEO)
 212
 213 #define GPIO_USB1_0             0x00010000      /* Power-On pin */
 214 #define GPIO_USB1_9             0x08            /* PX_~EN pin */
 215
 216 #define GPIO_EE_DO              0x10            /* PSC6_0 (DO) pin */
 217 #define GPIO_EE_CTS             0x20            /* PSC6_1 (CTS) pin */
 218 #define GPIO_EE_DI              0x10000000      /* PSC6_2 (DI) pin */
 219 #define GPIO_EE_CLK             0x20000000      /* PSC6_3 (CLK) pin */
 220
 221 #define GPT_GPIO_ON             0x00000034      /* GPT as simple GPIO, high */
 222
 223 /* ExBo I2C Addresses */
 224 #define EXBO_EE_I2C_ADDRESS     0x56
 225
 226 static void exbo_hw_init(void)
 227 {
 228         struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
 229         struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 230         struct mpc5xxx_wu_gpio *wu_gpio =
 231                                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 232         unsigned char val;
 233
 234         /* 1st, check if extension board is present */
 235         if (i2c_read(EXBO_EE_I2C_ADDRESS, 0, 1, &val, 1))
 236                 return;
 237
 238         /* configure IrDA pins (PSC6 port) as gpios */
 239         gpio->port_config &= 0xFF8FFFFF;
 240
 241         /* Init for USB1_0, EE_CLK and EE_DI - Low */
 242         setbits_be32(&gpio->simple_ddr,
 243                         GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
 244         clrbits_be32(&gpio->simple_ode,
 245                         GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
 246         clrbits_be32(&gpio->simple_dvo,
 247                         GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
 248         setbits_be32(&gpio->simple_gpioe,
 249                         GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
 250
 251         /* Init for EE_DO, EE_CTS - Input */
 252         clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
 253         setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);
 254
 255         /* Init for PX_~EN (USB1_9) - High */
 256         clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
 257         setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
 258         clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
 259         setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
 260         setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
 261
 262         /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
 263         out_be32(&gpt[0].emsr, GPT_GPIO_ON);
 264         /* Init for S Switch (GPIO4) - Timer_1 GPIO High */
 265         out_be32(&gpt[1].emsr, GPT_GPIO_ON);
 266
 267         /* Power-On camera supply */
 268         setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
 269 }
 270 #else
 271 static inline void exbo_hw_init(void) {}
 272 #endif /* CONFIG_VIDEO */
 273
 274 int board_early_init_r(void)
 275 {
 276 #ifdef CONFIG_MPC52XX_SPI
 277         struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
 278 #endif
 279         /*
 280          * Now, when we are in RAM, enable flash write access for detection
 281          * process.  Note that CS_BOOT cannot be cleared when executing in
 282          * flash.
 283          */
 284         /* disable CS_BOOT */
 285         clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
 286         /* enable CS1 */
 287         setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
 288         /* enable CS0 */
 289         setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
 290
 291         exbo_hw_init();
 292
 293 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
 294         /* Low level USB init, required for proper kernel operation */
 295         usb_cpu_init();
 296 #endif
 297 #ifdef CONFIG_MPC52XX_SPI
 298         /* GPT 6 Output Enable */
 299         out_be32(&gpt[6].emsr, 0x00000034);
 300         /* GPT 7 Output Enable */
 301         out_be32(&gpt[7].emsr, 0x00000034);
 302 #endif
 303
 304         return (0);
 305 }
 306
 307 void board_get_enetaddr (uchar * enet)
 308 {
 309         ushort read = 0;
 310         ushort addr_of_eth_addr = 0;
 311         ushort len_sys = 0;
 312         ushort len_sys_cfg = 0;
 313
 314         /* check identification word */
 315         eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
 316         if (read != EEPROM_IDENT)
 317                 return;
 318
 319         /* calculate offset of config area */
 320         eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
 321         eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
 322                 (uchar *)&len_sys_cfg, 2);
 323         addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
 324         if (addr_of_eth_addr >= EEPROM_LEN)
 325                 return;
 326
 327         eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
 328 }
 329
 330 int misc_init_r(void)
 331 {
 332         uchar enetaddr[6];
 333
 334         if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
 335                 board_get_enetaddr(enetaddr);
 336                 eth_setenv_enetaddr("ethaddr", enetaddr);
 337         }
 338
 339         return 0;
 340 }
 341
 342 #ifdef CONFIG_PCI
 343 static struct pci_controller hose;
 344
 345 extern void pci_mpc5xxx_init(struct pci_controller *);
 346
 347 void pci_init_board(void)
 348 {
 349         pci_mpc5xxx_init(&hose);
 350 }
 351 #endif
 352
 353 #ifdef CONFIG_CMD_IDE
 354
 355 #ifdef CONFIG_IDE_RESET
 356
 357 void init_ide_reset(void)
 358 {
 359         debug ("init_ide_reset\n");
 360
 361         /* set gpio output value to 1 */
 362         setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
 363         /* open drain output */
 364         setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
 365         /* direction output */
 366         setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
 367         /* enable gpio */
 368         setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 369
 370 }
 371
 372 void ide_set_reset(int idereset)
 373 {
 374         debug ("ide_reset(%d)\n", idereset);
 375
 376         /* set gpio output value to 0 */
 377         clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
 378         /* open drain output */
 379         setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
 380         /* direction output */
 381         setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
 382         /* enable gpio */
 383         setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 384
 385         udelay(10000);
 386
 387         /* set gpio output value to 1 */
 388         setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
 389         /* open drain output */
 390         setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
 391         /* direction output */
 392         setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
 393         /* enable gpio */
 394         setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 395 }
 396 #endif /* CONFIG_IDE_RESET */
 397 #endif /* CONFIG_CMD_IDE */
 398
 399 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 400 static void ft_delete_node(void *fdt, const char *compat)
 401 {
 402         int off = -1;
 403         int ret;
 404
 405         off = fdt_node_offset_by_compatible(fdt, -1, compat);
 406         if (off < 0) {
 407                 printf("Could not find %s node.\n", compat);
 408                 return;
 409         }
 410
 411         ret = fdt_del_node(fdt, off);
 412         if (ret < 0)
 413                 printf("Could not delete %s node.\n", compat);
 414 }
 415 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
 416 static void ft_adapt_flash_base(void *blob)
 417 {
 418         flash_info_t    *dev = &flash_info[0];
 419         int off;
 420         struct fdt_property *prop;
 421         int len;
 422         u32 *reg, *reg2;
 423
 424         off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
 425         if (off < 0) {
 426                 printf("Could not find fsl,mpc5200b-lpb node.\n");
 427                 return;
 428         }
 429
 430         /* found compatible property */
 431         prop = fdt_get_property_w(blob, off, "ranges", &len);
 432         if (prop) {
 433                 reg = reg2 = (u32 *)&prop->data[0];
 434
 435                 reg[2] = dev->start[0];
 436                 reg[3] = dev->size;
 437                 fdt_setprop(blob, off, "ranges", reg2, len);
 438         } else
 439                 printf("Could not find ranges\n");
 440 }
 441
 442 extern ulong flash_get_size (phys_addr_t base, int banknum);
 443
 444 /* Update the Flash Baseaddr settings */
 445 int update_flash_size (int flash_size)
 446 {
 447         volatile struct mpc5xxx_mmap_ctl *mm =
 448                 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
 449         flash_info_t    *dev;
 450         int     i;
 451         int size = 0;
 452         unsigned long base = 0x0;
 453         u32 *cs_reg = (u32 *)&mm->cs0_start;
 454
 455         for (i = 0; i < 2; i++) {
 456                 dev = &flash_info[i];
 457
 458                 if (dev->size) {
 459                         /* calculate new base addr for this chipselect */
 460                         base -= dev->size;
 461                         out_be32(cs_reg, START_REG(base));
 462                         cs_reg++;
 463                         out_be32(cs_reg, STOP_REG(base, dev->size));
 464                         cs_reg++;
 465                         /* recalculate the sectoraddr in the cfi driver */
 466                         size += flash_get_size(base, i);
 467                 }
 468         }
 469         flash_protect_default();
 470         gd->bd->bi_flashstart = base;
 471         return 0;
 472 }
 473 #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
 474
 475 void ft_board_setup(void *blob, bd_t *bd)
 476 {
 477         int phy_addr = CONFIG_PHY_ADDR;
 478         char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
 479
 480         ft_cpu_setup(blob, bd);
 481         /*
 482          * There are 2 RTC nodes in the DTS, so remove
 483          * the unneeded node here.
 484          */
 485 #if defined(CONFIG_DIGSY_REV5)
 486         ft_delete_node(blob, "dallas,ds1339");
 487 #else
 488         ft_delete_node(blob, "mc,rv3029c2");
 489 #endif
 490 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
 491 #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 492         /* Update reg property in all nor flash nodes too */
 493         fdt_fixup_nor_flash_size(blob);
 494 #endif
 495         ft_adapt_flash_base(blob);
 496 #endif
 497         /* fix up the phy address */
 498         do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
 499 }
 500 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */