board/digsy_mtc/digsy_mtc.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * (C) Copyright 2005-2009
   9  * Modified for InterControl digsyMTC MPC5200 board by
  10  * Frank Bodammer, GCD Hard- & Software GmbH,
  11  *                 frank.bodammer@gcd-solutions.de
  12  *
  13  * (C) Copyright 2009
  14  * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #include <common.h>
  36 #include <mpc5xxx.h>
  37 #include <net.h>
  38 #include <pci.h>
  39 #include <asm/processor.h>
  40 #include <asm/io.h>
  41 #include "eeprom.h"
  42 #include "is42s16800a-7t.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 extern int usb_cpu_init(void);
  47
  48 #ifndef CONFIG_SYS_RAMBOOT
  49 static void sdram_start(int hi_addr)
  50 {
  51         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  52         long control = SDRAM_CONTROL | hi_addr_bit;
  53
  54         /* unlock mode register */
  55         out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
  56
  57         /* precharge all banks */
  58         out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
  59
  60         /* auto refresh */
  61         out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
  62
  63         /* set mode register */
  64         out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
  65
  66         /* normal operation */
  67         out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
  68 }
  69 #endif
  70
  71 /*
  72  * ATTENTION: Although partially referenced initdram does NOT make real use
  73  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  74  *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  75  */
  76
  77 phys_size_t initdram(int board_type)
  78 {
  79         ulong dramsize = 0;
  80         ulong dramsize2 = 0;
  81         uint svr, pvr;
  82 #ifndef CONFIG_SYS_RAMBOOT
  83         ulong test1, test2;
  84
  85         /* setup SDRAM chip selects */
  86         out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
  87         out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
  88
  89         /* setup config registers */
  90         out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
  91         out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
  92
  93         /* find RAM size using SDRAM CS0 only */
  94         sdram_start(0);
  95         test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
  96         sdram_start(1);
  97         test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
  98         if (test1 > test2) {
  99                 sdram_start(0);
 100                 dramsize = test1;
 101         } else {
 102                 dramsize = test2;
 103         }
 104
 105         /* memory smaller than 1MB is impossible */
 106         if (dramsize < (1 << 20))
 107                 dramsize = 0;
 108
 109         /* set SDRAM CS0 size according to the amount of RAM found */
 110         if (dramsize > 0) {
 111                 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
 112                         (0x13 + __builtin_ffs(dramsize >> 20) - 1));
 113         } else {
 114                 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
 115         }
 116
 117         /* let SDRAM CS1 start right after CS0 */
 118         out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
 119
 120         /* find RAM size using SDRAM CS1 only */
 121         test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
 122                         0x08000000);
 123                 dramsize2 = test1;
 124
 125         /* memory smaller than 1MB is impossible */
 126         if (dramsize2 < (1 << 20))
 127                 dramsize2 = 0;
 128
 129         /* set SDRAM CS1 size according to the amount of RAM found */
 130         if (dramsize2 > 0) {
 131                 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
 132                         (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
 133         } else {
 134                 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
 135         }
 136
 137 #else /* CONFIG_SYS_RAMBOOT */
 138
 139         /* retrieve size of memory connected to SDRAM CS0 */
 140         dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
 141         if (dramsize >= 0x13)
 142                 dramsize = (1 << (dramsize - 0x13)) << 20;
 143         else
 144                 dramsize = 0;
 145
 146         /* retrieve size of memory connected to SDRAM CS1 */
 147         dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
 148         if (dramsize2 >= 0x13)
 149                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 150         else
 151                 dramsize2 = 0;
 152
 153 #endif /* CONFIG_SYS_RAMBOOT */
 154
 155         /*
 156          * On MPC5200B we need to set the special configuration delay in the
 157          * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 158          * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 159          *
 160          * "The SDelay should be written to a value of 0x00000004. It is
 161          * required to account for changes caused by normal wafer processing
 162          * parameters."
 163          */
 164         svr = get_svr();
 165         pvr = get_pvr();
 166         if ((SVR_MJREV(svr) >= 2) &&
 167             (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
 168                 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
 169
 170         return dramsize + dramsize2;
 171 }
 172
 173 int checkboard(void)
 174 {
 175         char *s = getenv("serial#");
 176
 177         puts ("Board: InterControl digsyMTC");
 178         if (s != NULL) {
 179                 puts(", ");
 180                 puts(s);
 181         }
 182         putc('\n');
 183
 184         return 0;
 185 }
 186
 187 int board_early_init_r(void)
 188 {
 189 #ifdef CONFIG_MPC52XX_SPI
 190         struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
 191 #endif
 192         /*
 193          * Now, when we are in RAM, enable flash write access for detection
 194          * process.  Note that CS_BOOT cannot be cleared when executing in
 195          * flash.
 196          */
 197         /* disable CS_BOOT */
 198         clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
 199         /* enable CS1 */
 200         setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
 201         /* enable CS0 */
 202         setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
 203
 204 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
 205         /* Low level USB init, required for proper kernel operation */
 206         usb_cpu_init();
 207 #endif
 208 #ifdef CONFIG_MPC52XX_SPI
 209         /* GPT 6 Output Enable */
 210         out_be32(&gpt[6].emsr, 0x00000034);
 211         /* GPT 7 Output Enable */
 212         out_be32(&gpt[7].emsr, 0x00000034);
 213 #endif
 214
 215         return (0);
 216 }
 217
 218 void board_get_enetaddr (uchar * enet)
 219 {
 220         ushort read = 0;
 221         ushort addr_of_eth_addr = 0;
 222         ushort len_sys = 0;
 223         ushort len_sys_cfg = 0;
 224
 225         /* check identification word */
 226         eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
 227         if (read != EEPROM_IDENT)
 228                 return;
 229
 230         /* calculate offset of config area */
 231         eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
 232         eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
 233                 (uchar *)&len_sys_cfg, 2);
 234         addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
 235         if (addr_of_eth_addr >= EEPROM_LEN)
 236                 return;
 237
 238         eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
 239 }
 240
 241 int misc_init_r(void)
 242 {
 243         uchar enetaddr[6];
 244
 245         if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
 246                 board_get_enetaddr(enetaddr);
 247                 eth_setenv_enetaddr("ethaddr", enetaddr);
 248         }
 249
 250         return 0;
 251 }
 252
 253 #ifdef CONFIG_PCI
 254 static struct pci_controller hose;
 255
 256 extern void pci_mpc5xxx_init(struct pci_controller *);
 257
 258 void pci_init_board(void)
 259 {
 260         pci_mpc5xxx_init(&hose);
 261 }
 262 #endif
 263
 264 #ifdef CONFIG_CMD_IDE
 265
 266 #ifdef CONFIG_IDE_RESET
 267
 268 void init_ide_reset(void)
 269 {
 270         debug ("init_ide_reset\n");
 271
 272         /* set gpio output value to 1 */
 273         setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
 274         /* open drain output */
 275         setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
 276         /* direction output */
 277         setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
 278         /* enable gpio */
 279         setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 280
 281 }
 282
 283 void ide_set_reset(int idereset)
 284 {
 285         debug ("ide_reset(%d)\n", idereset);
 286
 287         /* set gpio output value to 0 */
 288         clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
 289         /* open drain output */
 290         setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
 291         /* direction output */
 292         setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
 293         /* enable gpio */
 294         setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 295
 296         udelay(10000);
 297
 298         /* set gpio output value to 1 */
 299         setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
 300         /* open drain output */
 301         setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
 302         /* direction output */
 303         setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
 304         /* enable gpio */
 305         setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
 306 }
 307 #endif /* CONFIG_IDE_RESET */
 308
 309 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 310 void ft_board_setup(void *blob, bd_t *bd)
 311 {
 312         ft_cpu_setup(blob, bd);
 313 }
 314 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 315
 316 #endif /* CONFIG_CMD_IDE */