board/eXalion/eXalion.c

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2002
   6  * Torsten Demke, FORCE Computers GmbH. torsten.demke@fci.com
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <mpc824x.h>
  13 #include <asm/processor.h>
  14 #include <asm/io.h>
  15 #include <pci.h>
  16 #include <ide.h>
  17 #include <netdev.h>
  18 #include <timestamp.h>
  19 #include "piix_pci.h"
  20 #include "eXalion.h"
  21
  22 int checkboard (void)
  23 {
  24         ulong busfreq = get_bus_freq (0);
  25         char buf[32];
  26
  27         printf ("Board: eXalion MPC824x - CHRP (MAP B)\n");
  28         printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
  29         printf ("Local Bus:  %s MHz\n", strmhz (buf, busfreq));
  30
  31         return 0;
  32 }
  33
  34 int checkflash (void)
  35 {
  36         printf ("checkflash\n");
  37         flash_init ();
  38         return (0);
  39 }
  40
  41 phys_size_t initdram (int board_type)
  42 {
  43         int i, cnt;
  44         volatile uchar *base = CONFIG_SYS_SDRAM_BASE;
  45         volatile ulong *addr;
  46         ulong save[32];
  47         ulong val, ret = 0;
  48
  49         for (i = 0, cnt = (CONFIG_SYS_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
  50              cnt >>= 1) {
  51                 addr = (volatile ulong *) base + cnt;
  52                 save[i++] = *addr;
  53                 *addr = ~cnt;
  54         }
  55
  56         addr = (volatile ulong *) base;
  57         save[i] = *addr;
  58         *addr = 0;
  59
  60         if (*addr != 0) {
  61                 *addr = save[i];
  62                 goto Done;
  63         }
  64
  65         for (cnt = 1; cnt <= CONFIG_SYS_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
  66                 addr = (volatile ulong *) base + cnt;
  67                 val = *addr;
  68                 *addr = save[--i];
  69                 if (val != ~cnt) {
  70                         ulong new_bank0_end = cnt * sizeof (long) - 1;
  71                         ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
  72                         ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
  73
  74                         mear1 = (mear1 & 0xFFFFFF00) |
  75                                 ((new_bank0_end & MICR_ADDR_MASK) >>
  76                                  MICR_ADDR_SHIFT);
  77                         emear1 = (emear1 & 0xFFFFFF00) |
  78                                 ((new_bank0_end & MICR_ADDR_MASK) >>
  79                                  MICR_EADDR_SHIFT);
  80                         mpc824x_mpc107_setreg (MEAR1, mear1);
  81                         mpc824x_mpc107_setreg (EMEAR1, emear1);
  82
  83                         ret = cnt * sizeof (long);
  84                         goto Done;
  85                 }
  86         }
  87
  88         ret = CONFIG_SYS_MAX_RAM_SIZE;
  89       Done:
  90         return ret;
  91 }
  92
  93 int misc_init_r (void)
  94 {
  95         pci_dev_t bdf;
  96         u32 val32;
  97         u8 val8;
  98
  99         puts ("ISA:   ");
 100         bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_ISA_DEV_ID, 0);
 101         if (bdf == -1) {
 102                 puts ("Unable to find PIIX4 ISA bridge !\n");
 103                 hang ();
 104         }
 105
 106         /* set device for normal ISA instead EIO */
 107         pci_read_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, &val32);
 108         val32 |= 0x00000001;
 109         pci_write_config_dword (bdf, PCI_CFG_PIIX4_GENCFG, val32);
 110         printf ("PIIX4 ISA bridge (%d,%d,%d)\n", PCI_BUS (bdf),
 111                 PCI_DEV (bdf), PCI_FUNC (bdf));
 112
 113         puts ("ISA:   ");
 114         bdf = pci_find_device (PIIX4_VENDOR_ID, PIIX4_IDE_DEV_ID, 0);
 115         if (bdf == -1) {
 116                 puts ("Unable to find PIIX4 IDE controller !\n");
 117                 hang ();
 118         }
 119
 120         /* Init BMIBA register  */
 121         /* pci_read_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, &val32); */
 122         /* val32 |= 0x1000; */
 123         /* pci_write_config_dword(bdf, PCI_CFG_PIIX4_BMIBA, val32); */
 124
 125         /* Enable BUS master and IO access  */
 126         val32 = PCI_COMMAND_MASTER | PCI_COMMAND_IO;
 127         pci_write_config_dword (bdf, PCI_COMMAND, val32);
 128
 129         /* Set latency  */
 130         pci_read_config_byte (bdf, PCI_LATENCY_TIMER, &val8);
 131         val8 = 0x40;
 132         pci_write_config_byte (bdf, PCI_LATENCY_TIMER, val8);
 133
 134         /* Enable Primary ATA/IDE  */
 135         pci_read_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, &val32);
 136         /* val32 = 0xa307a307; */
 137         val32 = 0x00008000;
 138         pci_write_config_dword (bdf, PCI_CFG_PIIX4_IDETIM, val32);
 139
 140
 141         printf ("PIIX4 IDE controller (%d,%d,%d)\n", PCI_BUS (bdf),
 142                 PCI_DEV (bdf), PCI_FUNC (bdf));
 143
 144         /* Try to get FAT working... */
 145         /* fat_register_read(ide_read); */
 146
 147
 148         return (0);
 149 }
 150
 151 /*
 152  * Show/Init PCI devices on the specified bus number.
 153  */
 154
 155 void pci_eXalion_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 156 {
 157         unsigned char line;
 158
 159         switch (PCI_DEV (dev)) {
 160         case 16:
 161                 line = PCI_INT_A;
 162                 break;
 163         case 17:
 164                 line = PCI_INT_B;
 165                 break;
 166         case 18:
 167                 line = PCI_INT_C;
 168                 break;
 169         case 19:
 170                 line = PCI_INT_D;
 171                 break;
 172 #if defined (CONFIG_MPC8245)
 173         case 20:
 174                 line = PCI_INT_A;
 175                 break;
 176         case 21:
 177                 line = PCI_INT_B;
 178                 break;
 179         case 22:
 180                 line = PCI_INT_NA;
 181                 break;
 182 #endif
 183         default:
 184                 line = PCI_INT_A;
 185                 break;
 186         }
 187         pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, line);
 188 }
 189
 190
 191 /*
 192  * Initialize PCI Devices, report devices found.
 193  */
 194 #ifndef CONFIG_PCI_PNP
 195 #if defined (CONFIG_MPC8240)
 196 static struct pci_config_table pci_eXalion_config_table[] = {
 197         {
 198          /* Intel 82559ER ethernet controller */
 199          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
 200          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 201                                      PCI_ENET0_MEMADDR,
 202                                      PCI_COMMAND_MEMORY |
 203                                      PCI_COMMAND_MASTER}},
 204         {
 205          /* Intel 82371AB PIIX4 PCI to ISA bridge */
 206          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
 207          pci_cfgfunc_config_device, {0,
 208                                      0,
 209                                      PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
 210         {
 211          /* Intel 82371AB PIIX4 IDE controller */
 212          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x01,
 213          pci_cfgfunc_config_device, {0,
 214                                      0,
 215                                      PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
 216         {}
 217 };
 218 #elif defined (CONFIG_MPC8245)
 219 static struct pci_config_table pci_eXalion_config_table[] = {
 220         {
 221          /* Intel 82559ER ethernet controller */
 222          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 17, 0x00,
 223          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 224                                      PCI_ENET0_MEMADDR,
 225                                      PCI_COMMAND_MEMORY |
 226                                      PCI_COMMAND_MASTER}},
 227         {
 228          /* Intel 82559ER ethernet controller */
 229          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 18, 0x00,
 230          pci_cfgfunc_config_device, {PCI_ENET1_IOADDR,
 231                                      PCI_ENET1_MEMADDR,
 232                                      PCI_COMMAND_MEMORY |
 233                                      PCI_COMMAND_MASTER}},
 234         {
 235          /* Broadcom BCM5690 Gigabit switch */
 236          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 20, 0x00,
 237          pci_cfgfunc_config_device, {PCI_ENET2_IOADDR,
 238                                      PCI_ENET2_MEMADDR,
 239                                      PCI_COMMAND_MEMORY |
 240                                      PCI_COMMAND_MASTER}},
 241         {
 242          /* Broadcom BCM5690 Gigabit switch */
 243          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 21, 0x00,
 244          pci_cfgfunc_config_device, {PCI_ENET3_IOADDR,
 245                                      PCI_ENET3_MEMADDR,
 246                                      PCI_COMMAND_MEMORY |
 247                                      PCI_COMMAND_MASTER}},
 248         {
 249          /* Intel 82371AB PIIX4 PCI to ISA bridge */
 250          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x00,
 251          pci_cfgfunc_config_device, {0,
 252                                      0,
 253                                      PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
 254         {
 255          /* Intel 82371AB PIIX4 IDE controller */
 256          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x00, 22, 0x01,
 257          pci_cfgfunc_config_device, {0,
 258                                      0,
 259                                      PCI_COMMAND_IO | PCI_COMMAND_MASTER}},
 260         {}
 261 };
 262 #else
 263 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
 264 #endif
 265
 266 #endif /* #ifndef CONFIG_PCI_PNP */
 267
 268 struct pci_controller hose = {
 269 #ifndef CONFIG_PCI_PNP
 270         config_table:pci_eXalion_config_table,
 271         fixup_irq:pci_eXalion_fixup_irq,
 272 #endif
 273 };
 274
 275 void pci_init_board (void)
 276 {
 277         pci_mpc824x_init (&hose);
 278 }
 279
 280 int board_eth_init(bd_t *bis)
 281 {
 282         return pci_eth_init(bis);
 283 }