2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/sizes.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-ddr.h>
20 #include <asm/arch/mx6-pins.h>
21 #include <asm/arch/sys_proto.h>
23 #include <asm/mach-imx/iomux-v3.h>
24 #include <asm/mach-imx/video.h>
26 DECLARE_GLOBAL_DATA_PTR
;
28 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
29 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
30 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
32 static iomux_v3_cfg_t
const uart_pads
[] = {
34 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
35 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
37 IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
38 IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
48 #define IMX6DQ_DRIVE_STRENGTH 0x30
49 #define IMX6SDL_DRIVE_STRENGTH 0x28
51 /* configure MX6Q/DUAL mmdc DDR io registers */
52 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs
= {
53 .dram_sdqs0
= IMX6DQ_DRIVE_STRENGTH
,
54 .dram_sdqs1
= IMX6DQ_DRIVE_STRENGTH
,
55 .dram_sdqs2
= IMX6DQ_DRIVE_STRENGTH
,
56 .dram_sdqs3
= IMX6DQ_DRIVE_STRENGTH
,
57 .dram_sdqs4
= IMX6DQ_DRIVE_STRENGTH
,
58 .dram_sdqs5
= IMX6DQ_DRIVE_STRENGTH
,
59 .dram_sdqs6
= IMX6DQ_DRIVE_STRENGTH
,
60 .dram_sdqs7
= IMX6DQ_DRIVE_STRENGTH
,
61 .dram_dqm0
= IMX6DQ_DRIVE_STRENGTH
,
62 .dram_dqm1
= IMX6DQ_DRIVE_STRENGTH
,
63 .dram_dqm2
= IMX6DQ_DRIVE_STRENGTH
,
64 .dram_dqm3
= IMX6DQ_DRIVE_STRENGTH
,
65 .dram_dqm4
= IMX6DQ_DRIVE_STRENGTH
,
66 .dram_dqm5
= IMX6DQ_DRIVE_STRENGTH
,
67 .dram_dqm6
= IMX6DQ_DRIVE_STRENGTH
,
68 .dram_dqm7
= IMX6DQ_DRIVE_STRENGTH
,
69 .dram_cas
= IMX6DQ_DRIVE_STRENGTH
,
70 .dram_ras
= IMX6DQ_DRIVE_STRENGTH
,
71 .dram_sdclk_0
= IMX6DQ_DRIVE_STRENGTH
,
72 .dram_sdclk_1
= IMX6DQ_DRIVE_STRENGTH
,
73 .dram_reset
= IMX6DQ_DRIVE_STRENGTH
,
74 .dram_sdcke0
= IMX6DQ_DRIVE_STRENGTH
,
75 .dram_sdcke1
= IMX6DQ_DRIVE_STRENGTH
,
76 .dram_sdba2
= 0x00000000,
77 .dram_sdodt0
= IMX6DQ_DRIVE_STRENGTH
,
78 .dram_sdodt1
= IMX6DQ_DRIVE_STRENGTH
,
81 /* configure MX6Q/DUAL mmdc GRP io registers */
82 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs
= {
83 .grp_b0ds
= IMX6DQ_DRIVE_STRENGTH
,
84 .grp_b1ds
= IMX6DQ_DRIVE_STRENGTH
,
85 .grp_b2ds
= IMX6DQ_DRIVE_STRENGTH
,
86 .grp_b3ds
= IMX6DQ_DRIVE_STRENGTH
,
87 .grp_b4ds
= IMX6DQ_DRIVE_STRENGTH
,
88 .grp_b5ds
= IMX6DQ_DRIVE_STRENGTH
,
89 .grp_b6ds
= IMX6DQ_DRIVE_STRENGTH
,
90 .grp_b7ds
= IMX6DQ_DRIVE_STRENGTH
,
91 .grp_addds
= IMX6DQ_DRIVE_STRENGTH
,
92 .grp_ddrmode_ctl
= 0x00020000,
93 .grp_ddrpke
= 0x00000000,
94 .grp_ddrmode
= 0x00020000,
95 .grp_ctlds
= IMX6DQ_DRIVE_STRENGTH
,
96 .grp_ddr_type
= 0x000c0000,
99 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
100 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs
= {
101 .dram_sdclk_0
= IMX6SDL_DRIVE_STRENGTH
,
102 .dram_sdclk_1
= IMX6SDL_DRIVE_STRENGTH
,
103 .dram_cas
= IMX6SDL_DRIVE_STRENGTH
,
104 .dram_ras
= IMX6SDL_DRIVE_STRENGTH
,
105 .dram_reset
= IMX6SDL_DRIVE_STRENGTH
,
106 .dram_sdcke0
= IMX6SDL_DRIVE_STRENGTH
,
107 .dram_sdcke1
= IMX6SDL_DRIVE_STRENGTH
,
108 .dram_sdba2
= 0x00000000,
109 .dram_sdodt0
= IMX6SDL_DRIVE_STRENGTH
,
110 .dram_sdodt1
= IMX6SDL_DRIVE_STRENGTH
,
111 .dram_sdqs0
= IMX6SDL_DRIVE_STRENGTH
,
112 .dram_sdqs1
= IMX6SDL_DRIVE_STRENGTH
,
113 .dram_sdqs2
= IMX6SDL_DRIVE_STRENGTH
,
114 .dram_sdqs3
= IMX6SDL_DRIVE_STRENGTH
,
115 .dram_sdqs4
= IMX6SDL_DRIVE_STRENGTH
,
116 .dram_sdqs5
= IMX6SDL_DRIVE_STRENGTH
,
117 .dram_sdqs6
= IMX6SDL_DRIVE_STRENGTH
,
118 .dram_sdqs7
= IMX6SDL_DRIVE_STRENGTH
,
119 .dram_dqm0
= IMX6SDL_DRIVE_STRENGTH
,
120 .dram_dqm1
= IMX6SDL_DRIVE_STRENGTH
,
121 .dram_dqm2
= IMX6SDL_DRIVE_STRENGTH
,
122 .dram_dqm3
= IMX6SDL_DRIVE_STRENGTH
,
123 .dram_dqm4
= IMX6SDL_DRIVE_STRENGTH
,
124 .dram_dqm5
= IMX6SDL_DRIVE_STRENGTH
,
125 .dram_dqm6
= IMX6SDL_DRIVE_STRENGTH
,
126 .dram_dqm7
= IMX6SDL_DRIVE_STRENGTH
,
129 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
130 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
131 .grp_ddr_type
= 0x000c0000,
132 .grp_ddrmode_ctl
= 0x00020000,
133 .grp_ddrpke
= 0x00000000,
134 .grp_addds
= IMX6SDL_DRIVE_STRENGTH
,
135 .grp_ctlds
= IMX6SDL_DRIVE_STRENGTH
,
136 .grp_ddrmode
= 0x00020000,
137 .grp_b0ds
= IMX6SDL_DRIVE_STRENGTH
,
138 .grp_b1ds
= IMX6SDL_DRIVE_STRENGTH
,
139 .grp_b2ds
= IMX6SDL_DRIVE_STRENGTH
,
140 .grp_b3ds
= IMX6SDL_DRIVE_STRENGTH
,
141 .grp_b4ds
= IMX6SDL_DRIVE_STRENGTH
,
142 .grp_b5ds
= IMX6SDL_DRIVE_STRENGTH
,
143 .grp_b6ds
= IMX6SDL_DRIVE_STRENGTH
,
144 .grp_b7ds
= IMX6SDL_DRIVE_STRENGTH
,
148 static struct mx6_ddr3_cfg mt41j256
= {
162 static struct mx6_mmdc_calibration mx6dq_mmdc_calib
= {
163 .p0_mpwldectrl0
= 0x000E0009,
164 .p0_mpwldectrl1
= 0x0018000E,
165 .p1_mpwldectrl0
= 0x00000007,
166 .p1_mpwldectrl1
= 0x00000000,
167 .p0_mpdgctrl0
= 0x43280334,
168 .p0_mpdgctrl1
= 0x031C0314,
169 .p1_mpdgctrl0
= 0x4318031C,
170 .p1_mpdgctrl1
= 0x030C0258,
171 .p0_mprddlctl
= 0x3E343A40,
172 .p1_mprddlctl
= 0x383C3844,
173 .p0_mpwrdlctl
= 0x40404440,
174 .p1_mpwrdlctl
= 0x4C3E4446,
178 static struct mx6_ddr_sysinfo mem_q
= {
179 .ddr_type
= DDR_TYPE_DDR3
,
182 /* config for full 4GB range so that get_mem_size() works */
195 static struct mx6_mmdc_calibration mx6dl_mmdc_calib
= {
196 .p0_mpwldectrl0
= 0x001F0024,
197 .p0_mpwldectrl1
= 0x00110018,
198 .p1_mpwldectrl0
= 0x001F0024,
199 .p1_mpwldectrl1
= 0x00110018,
200 .p0_mpdgctrl0
= 0x4230022C,
201 .p0_mpdgctrl1
= 0x02180220,
202 .p1_mpdgctrl0
= 0x42440248,
203 .p1_mpdgctrl1
= 0x02300238,
204 .p0_mprddlctl
= 0x44444A48,
205 .p1_mprddlctl
= 0x46484A42,
206 .p0_mpwrdlctl
= 0x38383234,
207 .p1_mpwrdlctl
= 0x3C34362E,
211 static struct mx6_ddr_sysinfo mem_dl
= {
214 /* config for full 4GB range so that get_mem_size() works */
227 /* DDR 32bit 512MB */
228 static struct mx6_ddr_sysinfo mem_s
= {
231 /* config for full 4GB range so that get_mem_size() works */
243 #endif /* CONFIG_MX6QDL */
246 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs
= {
247 .grp_addds
= 0x00000030,
248 .grp_ddrmode_ctl
= 0x00020000,
249 .grp_b0ds
= 0x00000030,
250 .grp_ctlds
= 0x00000030,
251 .grp_b1ds
= 0x00000030,
252 .grp_ddrpke
= 0x00000000,
253 .grp_ddrmode
= 0x00020000,
254 .grp_ddr_type
= 0x000c0000,
257 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs
= {
258 .dram_dqm0
= 0x00000030,
259 .dram_dqm1
= 0x00000030,
260 .dram_ras
= 0x00000030,
261 .dram_cas
= 0x00000030,
262 .dram_odt0
= 0x00000030,
263 .dram_odt1
= 0x00000030,
264 .dram_sdba2
= 0x00000000,
265 .dram_sdclk_0
= 0x00000008,
266 .dram_sdqs0
= 0x00000038,
267 .dram_sdqs1
= 0x00000030,
268 .dram_reset
= 0x00000030,
271 static struct mx6_mmdc_calibration mx6_mmcd_calib
= {
272 .p0_mpwldectrl0
= 0x00070007,
273 .p0_mpdgctrl0
= 0x41490145,
274 .p0_mprddlctl
= 0x40404546,
275 .p0_mpwrdlctl
= 0x4040524D,
278 struct mx6_ddr_sysinfo ddr_sysinfo
= {
284 .rtt_nom
= 1, /* RTT_Nom = RZQ/2 */
285 .walat
= 1, /* Write additional latency */
286 .ralat
= 5, /* Read additional latency */
287 .mif3_mode
= 3, /* Command prediction working mode */
288 .bi_on
= 1, /* Bank interleaving enabled */
289 .sde_to_rst
= 0x10, /* 14 cycles, 200us (JEDEC default) */
290 .rst_to_cke
= 0x23, /* 33 cycles, 500us (JEDEC default) */
291 .ddr_type
= DDR_TYPE_DDR3
,
294 static struct mx6_ddr3_cfg mem_ddr
= {
299 #ifdef TARGET_MX6UL_ISIOT
310 #endif /* CONFIG_MX6UL */
312 static void ccgr_init(void)
314 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
317 writel(0x00003F3F, &ccm
->CCGR0
);
318 writel(0x0030FC00, &ccm
->CCGR1
);
319 writel(0x000FC000, &ccm
->CCGR2
);
320 writel(0x3F300000, &ccm
->CCGR3
);
321 writel(0xFF00F300, &ccm
->CCGR4
);
322 writel(0x0F0000C3, &ccm
->CCGR5
);
323 writel(0x000003CC, &ccm
->CCGR6
);
325 writel(0x00c03f3f, &ccm
->CCGR0
);
326 writel(0xfcffff00, &ccm
->CCGR1
);
327 writel(0x0cffffcc, &ccm
->CCGR2
);
328 writel(0x3f3c3030, &ccm
->CCGR3
);
329 writel(0xff00fffc, &ccm
->CCGR4
);
330 writel(0x033f30ff, &ccm
->CCGR5
);
331 writel(0x00c00fff, &ccm
->CCGR6
);
335 static void spl_dram_init(void)
339 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
340 mx6_dram_cfg(&mem_s
, &mx6dl_mmdc_calib
, &mt41j256
);
341 } else if (is_mx6dl()) {
342 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
343 mx6_dram_cfg(&mem_dl
, &mx6dl_mmdc_calib
, &mt41j256
);
344 } else if (is_mx6dq()) {
345 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs
, &mx6dq_grp_ioregs
);
346 mx6_dram_cfg(&mem_q
, &mx6dq_mmdc_calib
, &mt41j256
);
349 mx6ul_dram_iocfg(mem_ddr
.width
, &mx6_ddr_ioregs
, &mx6_grp_ioregs
);
350 mx6_dram_cfg(&ddr_sysinfo
, &mx6_mmcd_calib
, &mem_ddr
);
356 void board_init_f(ulong dummy
)
360 /* setup AIPS and disable watchdog */
366 SETUP_IOMUX_PADS(uart_pads
);
371 /* UART clocks enabled and gd valid - init serial console */
372 preloader_console_init();
374 /* DDR initialization */
378 memset(__bss_start
, 0, __bss_end
- __bss_start
);
380 /* load/boot image from boot device */
381 board_init_r(NULL
, 0);