board/engicam/geam6ul/geam6ul.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <mmc.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <linux/sizes.h>
  15
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/crm_regs.h>
  18 #include <asm/arch/iomux.h>
  19 #include <asm/arch/mx6-pins.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/imx-common/iomux-v3.h>
  22
  23 #include "../common/board.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #ifdef CONFIG_NAND_MXS
  28
  29 #define GPMI_PAD_CTRL0          (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  30 #define GPMI_PAD_CTRL1          (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  31                                 PAD_CTL_SRE_FAST)
  32 #define GPMI_PAD_CTRL2          (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  33
  34 static iomux_v3_cfg_t const nand_pads[] = {
  35         IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  36         IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  37         IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  38         IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  39         IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  40         IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  41         IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  42         IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  43         IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  44         IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  45         IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  46         IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  47         IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  48         IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  49         IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  50 };
  51
  52 void setup_gpmi_nand(void)
  53 {
  54         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  55
  56         /* config gpmi nand iomux */
  57         SETUP_IOMUX_PADS(nand_pads);
  58
  59         clrbits_le32(&mxc_ccm->CCGR4,
  60                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  61                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  62                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  63                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  64                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  65
  66         /*
  67          * config gpmi and bch clock to 100 MHz
  68          * bch/gpmi select PLL2 PFD2 400M
  69          * 100M = 400M / 4
  70          */
  71         clrbits_le32(&mxc_ccm->cscmr1,
  72                      MXC_CCM_CSCMR1_BCH_CLK_SEL |
  73                      MXC_CCM_CSCMR1_GPMI_CLK_SEL);
  74         clrsetbits_le32(&mxc_ccm->cscdr1,
  75                         MXC_CCM_CSCDR1_BCH_PODF_MASK |
  76                         MXC_CCM_CSCDR1_GPMI_PODF_MASK,
  77                         (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  78                         (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  79
  80         /* enable gpmi and bch clock gating */
  81         setbits_le32(&mxc_ccm->CCGR4,
  82                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  83                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  84                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  85                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  86                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  87
  88         /* enable apbh clock gating */
  89         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  90 }
  91 #endif /* CONFIG_NAND_MXS */
  92
  93 int board_late_init(void)
  94 {
  95         switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
  96                         IMX6_BMODE_SHIFT) {
  97         case IMX6_BMODE_SD:
  98         case IMX6_BMODE_ESD:
  99 #ifdef CONFIG_ENV_IS_IN_MMC
 100                 mmc_late_init();
 101 #endif
 102                 setenv("modeboot", "mmcboot");
 103                 break;
 104         case IMX6_BMODE_NAND:
 105                 setenv("modeboot", "nandboot");
 106                 break;
 107         default:
 108                 setenv("modeboot", "");
 109                 break;
 110         }
 111
 112         if (is_mx6ul())
 113                 setenv("fdt_file", "imx6ul-geam-kit.dtb");
 114
 115         return 0;
 116 }
 117
 118 #ifdef CONFIG_SPL_BUILD
 119 /* MMC board initialization is needed till adding DM support in SPL */
 120 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 121 #include <mmc.h>
 122 #include <fsl_esdhc.h>
 123
 124 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 125         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 126         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 127
 128 static iomux_v3_cfg_t const usdhc1_pads[] = {
 129         IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 130         IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 131         IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 132         IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 133         IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 134         IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 135
 136         /* VSELECT */
 137         IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 138         /* CD */
 139         IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 140         /* RST_B */
 141         IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 142 };
 143
 144 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 1)
 145
 146 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 147         {USDHC1_BASE_ADDR, 0, 4},
 148 };
 149
 150 int board_mmc_getcd(struct mmc *mmc)
 151 {
 152         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 153         int ret = 0;
 154
 155         switch (cfg->esdhc_base) {
 156         case USDHC1_BASE_ADDR:
 157                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 158                 break;
 159         }
 160
 161         return ret;
 162 }
 163
 164 int board_mmc_init(bd_t *bis)
 165 {
 166         int i, ret;
 167
 168         /*
 169         * According to the board_mmc_init() the following map is done:
 170         * (U-boot device node)    (Physical Port)
 171         * mmc0                          USDHC1
 172         */
 173         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 174                 switch (i) {
 175                 case 0:
 176                         SETUP_IOMUX_PADS(usdhc1_pads);
 177                         gpio_direction_input(USDHC1_CD_GPIO);
 178                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 179                         break;
 180                 default:
 181                         printf("Warning - USDHC%d controller not supporting\n",
 182                                i + 1);
 183                         return 0;
 184                 }
 185
 186                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 187                 if (ret) {
 188                         printf("Warning: failed to initialize mmc dev %d\n", i);
 189                         return ret;
 190                 }
 191         }
 192
 193         return 0;
 194 }
 195 #endif /* CONFIG_FSL_ESDHC */
 196 #endif /* CONFIG_SPL_BUILD */