board/engicam/geam6ul/geam6ul.c

   1 /*
   2  * Copyright (C) 2016 Amarula Solutions B.V.
   3  * Copyright (C) 2016 Engicam S.r.l.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10
  11 #include <asm/io.h>
  12 #include <asm/gpio.h>
  13 #include <linux/sizes.h>
  14
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/iomux.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/imx-common/iomux-v3.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  25         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  26         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  27
  28 static iomux_v3_cfg_t const uart1_pads[] = {
  29         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  30         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  31 };
  32
  33 int board_early_init_f(void)
  34 {
  35         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  36
  37         return 0;
  38 }
  39
  40 #ifdef CONFIG_NAND_MXS
  41
  42 #define GPMI_PAD_CTRL0          (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  43 #define GPMI_PAD_CTRL1          (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  44                                 PAD_CTL_SRE_FAST)
  45 #define GPMI_PAD_CTRL2          (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  46
  47 static iomux_v3_cfg_t const nand_pads[] = {
  48         MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  49         MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  50         MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  51         MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  52         MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  53         MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  54         MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  55         MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  56         MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  57         MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  58         MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  59         MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  60         MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  61         MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  62         MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  63 };
  64
  65 static void setup_gpmi_nand(void)
  66 {
  67         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  68
  69         /* config gpmi nand iomux */
  70         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  71
  72         clrbits_le32(&mxc_ccm->CCGR4,
  73                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  74                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  75                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  76                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  77                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  78
  79         /*
  80          * config gpmi and bch clock to 100 MHz
  81          * bch/gpmi select PLL2 PFD2 400M
  82          * 100M = 400M / 4
  83          */
  84         clrbits_le32(&mxc_ccm->cscmr1,
  85                      MXC_CCM_CSCMR1_BCH_CLK_SEL |
  86                      MXC_CCM_CSCMR1_GPMI_CLK_SEL);
  87         clrsetbits_le32(&mxc_ccm->cscdr1,
  88                         MXC_CCM_CSCDR1_BCH_PODF_MASK |
  89                         MXC_CCM_CSCDR1_GPMI_PODF_MASK,
  90                         (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  91                         (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  92
  93         /* enable gpmi and bch clock gating */
  94         setbits_le32(&mxc_ccm->CCGR4,
  95                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  96                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  97                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  98                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  99                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 100
 101         /* enable apbh clock gating */
 102         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 103 }
 104 #endif /* CONFIG_NAND_MXS */
 105
 106 int board_init(void)
 107 {
 108         /* Address of boot parameters */
 109         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 110
 111 #ifdef CONFIG_NAND_MXS
 112         setup_gpmi_nand();
 113 #endif
 114
 115         return 0;
 116 }
 117
 118 int dram_init(void)
 119 {
 120         gd->ram_size = imx_ddr_size();
 121
 122         return 0;
 123 }
 124
 125 #ifdef CONFIG_SPL_BUILD
 126 #include <libfdt.h>
 127 #include <spl.h>
 128
 129 #include <asm/arch/crm_regs.h>
 130 #include <asm/arch/mx6-ddr.h>
 131
 132 /* MMC board initialization is needed till adding DM support in SPL */
 133 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
 134 #include <mmc.h>
 135 #include <fsl_esdhc.h>
 136
 137 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
 138         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
 139         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 140
 141 static iomux_v3_cfg_t const usdhc1_pads[] = {
 142         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148
 149         /* VSELECT */
 150         MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151         /* CD */
 152         MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 153         /* RST_B */
 154         MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 155 };
 156
 157 #define USDHC1_CD_GPIO  IMX_GPIO_NR(1, 1)
 158
 159 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 160         {USDHC1_BASE_ADDR, 0, 4},
 161 };
 162
 163 int board_mmc_getcd(struct mmc *mmc)
 164 {
 165         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 166         int ret = 0;
 167
 168         switch (cfg->esdhc_base) {
 169         case USDHC1_BASE_ADDR:
 170                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 171                 break;
 172         }
 173
 174         return ret;
 175 }
 176
 177 int board_mmc_init(bd_t *bis)
 178 {
 179         int i, ret;
 180
 181         /*
 182         * According to the board_mmc_init() the following map is done:
 183         * (U-boot device node)    (Physical Port)
 184         * mmc0                          USDHC1
 185         */
 186         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 187                 switch (i) {
 188                 case 0:
 189                         imx_iomux_v3_setup_multiple_pads(
 190                                 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 191                         gpio_direction_input(USDHC1_CD_GPIO);
 192                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 193                         break;
 194                 default:
 195                         printf("Warning - USDHC%d controller not supporting\n",
 196                                i + 1);
 197                         return 0;
 198                 }
 199
 200                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 201                 if (ret) {
 202                         printf("Warning: failed to initialize mmc dev %d\n", i);
 203                         return ret;
 204                 }
 205         }
 206
 207         return 0;
 208 }
 209 #endif /* CONFIG_FSL_ESDHC */
 210
 211 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 212         .grp_addds = 0x00000030,
 213         .grp_ddrmode_ctl = 0x00020000,
 214         .grp_b0ds = 0x00000030,
 215         .grp_ctlds = 0x00000030,
 216         .grp_b1ds = 0x00000030,
 217         .grp_ddrpke = 0x00000000,
 218         .grp_ddrmode = 0x00020000,
 219         .grp_ddr_type = 0x000c0000,
 220 };
 221
 222 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
 223         .dram_dqm0 = 0x00000030,
 224         .dram_dqm1 = 0x00000030,
 225         .dram_ras = 0x00000030,
 226         .dram_cas = 0x00000030,
 227         .dram_odt0 = 0x00000030,
 228         .dram_odt1 = 0x00000030,
 229         .dram_sdba2 = 0x00000000,
 230         .dram_sdclk_0 = 0x00000008,
 231         .dram_sdqs0 = 0x00000038,
 232         .dram_sdqs1 = 0x00000030,
 233         .dram_reset = 0x00000030,
 234 };
 235
 236 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
 237         .p0_mpwldectrl0 = 0x00070007,
 238         .p0_mpdgctrl0 = 0x41490145,
 239         .p0_mprddlctl = 0x40404546,
 240         .p0_mpwrdlctl = 0x4040524D,
 241 };
 242
 243 struct mx6_ddr_sysinfo ddr_sysinfo = {
 244         .dsize = 0,
 245         .cs_density = 20,
 246         .ncs = 1,
 247         .cs1_mirror = 0,
 248         .rtt_wr = 2,
 249         .rtt_nom = 1,           /* RTT_Nom = RZQ/2 */
 250         .walat = 1,             /* Write additional latency */
 251         .ralat = 5,             /* Read additional latency */
 252         .mif3_mode = 3,         /* Command prediction working mode */
 253         .bi_on = 1,             /* Bank interleaving enabled */
 254         .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 255         .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 256         .ddr_type = DDR_TYPE_DDR3,
 257 };
 258
 259 static struct mx6_ddr3_cfg mem_ddr = {
 260         .mem_speed = 800,
 261         .density = 4,
 262         .width = 16,
 263         .banks = 8,
 264         .rowaddr = 13,
 265         .coladdr = 10,
 266         .pagesz = 2,
 267         .trcd = 1375,
 268         .trcmin = 4875,
 269         .trasmin = 3500,
 270 };
 271
 272 static void ccgr_init(void)
 273 {
 274         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 275
 276         writel(0xFFFFFFFF, &ccm->CCGR0);
 277         writel(0xFFFFFFFF, &ccm->CCGR1);
 278         writel(0xFFFFFFFF, &ccm->CCGR2);
 279         writel(0xFFFFFFFF, &ccm->CCGR3);
 280         writel(0xFFFFFFFF, &ccm->CCGR4);
 281         writel(0xFFFFFFFF, &ccm->CCGR5);
 282         writel(0xFFFFFFFF, &ccm->CCGR6);
 283         writel(0xFFFFFFFF, &ccm->CCGR7);
 284 }
 285
 286 static void spl_dram_init(void)
 287 {
 288         mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 289         mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 290 }
 291
 292 void board_init_f(ulong dummy)
 293 {
 294         /* setup AIPS and disable watchdog */
 295         arch_cpu_init();
 296
 297         ccgr_init();
 298
 299         /* iomux and setup of i2c */
 300         board_early_init_f();
 301
 302         /* setup GP timer */
 303         timer_init();
 304
 305         /* UART clocks enabled and gd valid - init serial console */
 306         preloader_console_init();
 307
 308         /* DDR initialization */
 309         spl_dram_init();
 310
 311         /* Clear the BSS. */
 312         memset(__bss_start, 0, __bss_end - __bss_start);
 313
 314         /* load/boot image from boot device */
 315         board_init_r(NULL, 0);
 316 }
 317 #endif /* CONFIG_SPL_BUILD */