2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/sizes.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/iomux.h>
18 #include <asm/arch/mx6-pins.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/imx-common/iomux-v3.h>
21 #include <asm/imx-common/video.h>
23 DECLARE_GLOBAL_DATA_PTR
;
25 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
26 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
27 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
29 static iomux_v3_cfg_t
const uart4_pads
[] = {
30 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
31 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
34 #ifdef CONFIG_NAND_MXS
36 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
37 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
39 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
41 iomux_v3_cfg_t gpmi_pads
[] = {
42 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
43 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
44 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
45 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL0
)),
46 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
47 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
48 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
49 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
50 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
51 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
52 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
53 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
54 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
55 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
56 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
)),
59 static void setup_gpmi_nand(void)
61 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
63 /* config gpmi nand iomux */
64 SETUP_IOMUX_PADS(gpmi_pads
);
66 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
67 clrbits_le32(&mxc_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
69 /* config gpmi and bch clock to 100 MHz */
70 clrsetbits_le32(&mxc_ccm
->cs2cdr
,
71 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK
|
72 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK
|
73 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK
,
74 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
75 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
76 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
78 /* enable ENFC_CLK_ROOT clock */
79 setbits_le32(&mxc_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
81 /* enable gpmi and bch clock gating */
82 setbits_le32(&mxc_ccm
->CCGR4
,
83 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK
|
84 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK
|
85 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
|
86 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK
|
87 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET
);
89 /* enable apbh clock gating */
90 setbits_le32(&mxc_ccm
->CCGR0
, MXC_CCM_CCGR0_APBHDMA_MASK
);
94 #if defined(CONFIG_VIDEO_IPUV3)
95 static iomux_v3_cfg_t
const rgb_pads
[] = {
96 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK
),
97 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15
),
98 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02
),
99 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03
),
100 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00
),
101 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01
),
102 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02
),
103 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03
),
104 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04
),
105 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05
),
106 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06
),
107 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07
),
108 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08
),
109 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09
),
110 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10
),
111 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11
),
112 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12
),
113 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13
),
114 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14
),
115 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15
),
116 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16
),
117 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17
),
120 static void enable_rgb(struct display_info_t
const *dev
)
122 SETUP_IOMUX_PADS(rgb_pads
);
125 struct display_info_t
const displays
[] = {
129 .pixfmt
= IPU_PIX_FMT_RGB666
,
131 .enable
= enable_rgb
,
145 .vmode
= FB_VMODE_NONINTERLACED
150 size_t display_count
= ARRAY_SIZE(displays
);
152 static void setup_display(void)
154 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
155 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
160 /* Turn on LDB0,IPU,IPU DI0 clocks */
161 reg
= __raw_readl(&mxc_ccm
->CCGR3
);
162 reg
|= (MXC_CCM_CCGR3_LDB_DI0_MASK
| 0xffff);
163 writel(reg
, &mxc_ccm
->CCGR3
);
165 /* set LDB0, LDB1 clk select to 011/011 */
166 reg
= readl(&mxc_ccm
->cs2cdr
);
167 reg
&= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|
168 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
);
169 reg
|= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
) |
170 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
);
171 writel(reg
, &mxc_ccm
->cs2cdr
);
173 reg
= readl(&mxc_ccm
->cscmr2
);
174 reg
|= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV
;
175 writel(reg
, &mxc_ccm
->cscmr2
);
177 reg
= readl(&mxc_ccm
->chsccdr
);
178 reg
|= (CHSCCDR_CLK_SEL_LDB_DI0
<<
179 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET
);
180 writel(reg
, &mxc_ccm
->chsccdr
);
182 reg
= IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
|
183 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
|
184 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
|
185 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
|
186 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
|
187 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|
188 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
|
189 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
|
190 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0
;
191 writel(reg
, &iomux
->gpr
[2]);
193 reg
= readl(&iomux
->gpr
[3]);
194 reg
= (reg
& ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
) |
195 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<
196 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET
);
197 writel(reg
, &iomux
->gpr
[3]);
199 #endif /* CONFIG_VIDEO_IPUV3 */
201 int board_early_init_f(void)
203 SETUP_IOMUX_PADS(uart4_pads
);
210 /* Address of boot parameters */
211 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
213 #ifdef CONFIG_NAND_MXS
217 #ifdef CONFIG_VIDEO_IPUV3
226 gd
->ram_size
= imx_ddr_size();
231 #ifdef CONFIG_SPL_BUILD
235 #include <asm/arch/crm_regs.h>
236 #include <asm/arch/mx6-ddr.h>
238 /* MMC board initialization is needed till adding DM support in SPL */
239 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
241 #include <fsl_esdhc.h>
243 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
244 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
245 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
247 static iomux_v3_cfg_t
const usdhc1_pads
[] = {
248 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
249 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
250 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
251 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
252 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
253 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
254 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01
| MUX_PAD_CTRL(NO_PAD_CTRL
)),/* CD */
257 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
259 struct fsl_esdhc_cfg usdhc_cfg
[1] = {
260 {USDHC1_BASE_ADDR
, 0, 4},
263 int board_mmc_getcd(struct mmc
*mmc
)
265 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
268 switch (cfg
->esdhc_base
) {
269 case USDHC1_BASE_ADDR
:
270 ret
= !gpio_get_value(USDHC1_CD_GPIO
);
277 int board_mmc_init(bd_t
*bis
)
282 * According to the board_mmc_init() the following map is done:
283 * (U-boot device node) (Physical Port)
286 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
289 SETUP_IOMUX_PADS(usdhc1_pads
);
290 gpio_direction_input(USDHC1_CD_GPIO
);
291 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
294 printf("Warning - USDHC%d controller not supporting\n",
299 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
301 printf("Warning: failed to initialize mmc dev %d\n", i
);
316 #define IMX6DQ_DRIVE_STRENGTH 0x30
317 #define IMX6SDL_DRIVE_STRENGTH 0x28
319 /* configure MX6Q/DUAL mmdc DDR io registers */
320 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs
= {
339 .dram_sdclk_0
= 0x30,
340 .dram_sdclk_1
= 0x30,
342 .dram_sdcke0
= 0x3000,
343 .dram_sdcke1
= 0x3000,
344 .dram_sdba2
= 0x00000000,
349 /* configure MX6Q/DUAL mmdc GRP io registers */
350 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs
= {
360 .grp_ddrmode_ctl
= 0x00020000,
361 .grp_ddrpke
= 0x00000000,
362 .grp_ddrmode
= 0x00020000,
364 .grp_ddr_type
= 0x000c0000,
367 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
368 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs
= {
369 .dram_sdclk_0
= 0x30,
370 .dram_sdclk_1
= 0x30,
376 .dram_sdba2
= 0x00000000,
397 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
398 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
399 .grp_ddr_type
= 0x000c0000,
400 .grp_ddrmode_ctl
= 0x00020000,
401 .grp_ddrpke
= 0x00000000,
404 .grp_ddrmode
= 0x00020000,
416 static struct mx6_ddr3_cfg mt41j256
= {
430 static struct mx6_mmdc_calibration mx6dq_mmdc_calib
= {
431 .p0_mpwldectrl0
= 0x000E0009,
432 .p0_mpwldectrl1
= 0x0018000E,
433 .p1_mpwldectrl0
= 0x00000007,
434 .p1_mpwldectrl1
= 0x00000000,
435 .p0_mpdgctrl0
= 0x43280334,
436 .p0_mpdgctrl1
= 0x031C0314,
437 .p1_mpdgctrl0
= 0x4318031C,
438 .p1_mpdgctrl1
= 0x030C0258,
439 .p0_mprddlctl
= 0x3E343A40,
440 .p1_mprddlctl
= 0x383C3844,
441 .p0_mpwrdlctl
= 0x40404440,
442 .p1_mpwrdlctl
= 0x4C3E4446,
446 static struct mx6_ddr_sysinfo mem_q
= {
447 .ddr_type
= DDR_TYPE_DDR3
,
450 /* config for full 4GB range so that get_mem_size() works */
463 static struct mx6_mmdc_calibration mx6dl_mmdc_calib
= {
464 .p0_mpwldectrl0
= 0x001F0024,
465 .p0_mpwldectrl1
= 0x00110018,
466 .p1_mpwldectrl0
= 0x001F0024,
467 .p1_mpwldectrl1
= 0x00110018,
468 .p0_mpdgctrl0
= 0x4230022C,
469 .p0_mpdgctrl1
= 0x02180220,
470 .p1_mpdgctrl0
= 0x42440248,
471 .p1_mpdgctrl1
= 0x02300238,
472 .p0_mprddlctl
= 0x44444A48,
473 .p1_mprddlctl
= 0x46484A42,
474 .p0_mpwrdlctl
= 0x38383234,
475 .p1_mpwrdlctl
= 0x3C34362E,
479 static struct mx6_ddr_sysinfo mem_dl
= {
482 /* config for full 4GB range so that get_mem_size() works */
495 /* DDR 32bit 512MB */
496 static struct mx6_ddr_sysinfo mem_s
= {
499 /* config for full 4GB range so that get_mem_size() works */
512 static void ccgr_init(void)
514 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
516 writel(0x00003F3F, &ccm
->CCGR0
);
517 writel(0x0030FC00, &ccm
->CCGR1
);
518 writel(0x000FC000, &ccm
->CCGR2
);
519 writel(0x3F300000, &ccm
->CCGR3
);
520 writel(0xFF00F300, &ccm
->CCGR4
);
521 writel(0x0F0000C3, &ccm
->CCGR5
);
522 writel(0x000003CC, &ccm
->CCGR6
);
525 static void gpr_init(void)
527 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
529 /* enable AXI cache for VDOA/VPU/IPU */
530 writel(0xF00000CF, &iomux
->gpr
[4]);
531 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
532 writel(0x007F007F, &iomux
->gpr
[6]);
533 writel(0x007F007F, &iomux
->gpr
[7]);
536 static void spl_dram_init(void)
539 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
540 mx6_dram_cfg(&mem_s
, &mx6dl_mmdc_calib
, &mt41j256
);
541 } else if (is_mx6dl()) {
542 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
543 mx6_dram_cfg(&mem_dl
, &mx6dl_mmdc_calib
, &mt41j256
);
544 } else if (is_mx6dq()) {
545 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs
, &mx6dq_grp_ioregs
);
546 mx6_dram_cfg(&mem_q
, &mx6dq_mmdc_calib
, &mt41j256
);
552 void board_init_f(ulong dummy
)
556 /* setup AIPS and disable watchdog */
562 board_early_init_f();
567 /* UART clocks enabled and gd valid - init serial console */
568 preloader_console_init();
570 /* DDR initialization */
574 memset(__bss_start
, 0, __bss_end
- __bss_start
);
576 /* load/boot image from boot device */
577 board_init_r(NULL
, 0);