2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <fsl_esdhc.h>
15 #include <linux/sizes.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/imx-common/iomux-v3.h>
23 DECLARE_GLOBAL_DATA_PTR
;
25 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
26 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
27 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
29 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
30 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
31 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33 static iomux_v3_cfg_t
const uart4_pads
[] = {
34 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
35 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
38 static iomux_v3_cfg_t
const usdhc1_pads
[] = {
39 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
40 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
41 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
42 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
43 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
44 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
45 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01
| MUX_PAD_CTRL(NO_PAD_CTRL
)),/* CD */
48 #ifdef CONFIG_FSL_ESDHC
49 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
51 struct fsl_esdhc_cfg usdhc_cfg
[1] = {
52 {USDHC1_BASE_ADDR
, 0, 4},
55 int board_mmc_getcd(struct mmc
*mmc
)
57 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
60 switch (cfg
->esdhc_base
) {
61 case USDHC1_BASE_ADDR
:
62 ret
= !gpio_get_value(USDHC1_CD_GPIO
);
69 int board_mmc_init(bd_t
*bis
)
74 * According to the board_mmc_init() the following map is done:
75 * (U-boot device node) (Physical Port)
78 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
81 SETUP_IOMUX_PADS(usdhc1_pads
);
82 gpio_direction_input(USDHC1_CD_GPIO
);
83 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
86 printf("Warning - USDHC%d controller not supporting\n",
91 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
93 printf("Warning: failed to initialize mmc dev %d\n", i
);
102 int board_early_init_f(void)
104 SETUP_IOMUX_PADS(uart4_pads
);
111 /* Address of boot parameters */
112 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
119 gd
->ram_size
= imx_ddr_size();
124 #ifdef CONFIG_SPL_BUILD
128 #include <asm/arch/crm_regs.h>
129 #include <asm/arch/mx6-ddr.h>
137 #define IMX6DQ_DRIVE_STRENGTH 0x30
138 #define IMX6SDL_DRIVE_STRENGTH 0x28
140 /* configure MX6Q/DUAL mmdc DDR io registers */
141 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs
= {
160 .dram_sdclk_0
= 0x30,
161 .dram_sdclk_1
= 0x30,
163 .dram_sdcke0
= 0x3000,
164 .dram_sdcke1
= 0x3000,
165 .dram_sdba2
= 0x00000000,
170 /* configure MX6Q/DUAL mmdc GRP io registers */
171 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs
= {
181 .grp_ddrmode_ctl
= 0x00020000,
182 .grp_ddrpke
= 0x00000000,
183 .grp_ddrmode
= 0x00020000,
185 .grp_ddr_type
= 0x000c0000,
188 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
189 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs
= {
190 .dram_sdclk_0
= 0x30,
191 .dram_sdclk_1
= 0x30,
197 .dram_sdba2
= 0x00000000,
218 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
219 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
220 .grp_ddr_type
= 0x000c0000,
221 .grp_ddrmode_ctl
= 0x00020000,
222 .grp_ddrpke
= 0x00000000,
225 .grp_ddrmode
= 0x00020000,
237 static struct mx6_ddr3_cfg mt41j256
= {
251 static struct mx6_mmdc_calibration mx6dq_mmdc_calib
= {
252 .p0_mpwldectrl0
= 0x000E0009,
253 .p0_mpwldectrl1
= 0x0018000E,
254 .p1_mpwldectrl0
= 0x00000007,
255 .p1_mpwldectrl1
= 0x00000000,
256 .p0_mpdgctrl0
= 0x43280334,
257 .p0_mpdgctrl1
= 0x031C0314,
258 .p1_mpdgctrl0
= 0x4318031C,
259 .p1_mpdgctrl1
= 0x030C0258,
260 .p0_mprddlctl
= 0x3E343A40,
261 .p1_mprddlctl
= 0x383C3844,
262 .p0_mpwrdlctl
= 0x40404440,
263 .p1_mpwrdlctl
= 0x4C3E4446,
267 static struct mx6_ddr_sysinfo mem_q
= {
268 .ddr_type
= DDR_TYPE_DDR3
,
271 /* config for full 4GB range so that get_mem_size() works */
284 static struct mx6_mmdc_calibration mx6dl_mmdc_calib
= {
285 .p0_mpwldectrl0
= 0x001F0024,
286 .p0_mpwldectrl1
= 0x00110018,
287 .p1_mpwldectrl0
= 0x001F0024,
288 .p1_mpwldectrl1
= 0x00110018,
289 .p0_mpdgctrl0
= 0x4230022C,
290 .p0_mpdgctrl1
= 0x02180220,
291 .p1_mpdgctrl0
= 0x42440248,
292 .p1_mpdgctrl1
= 0x02300238,
293 .p0_mprddlctl
= 0x44444A48,
294 .p1_mprddlctl
= 0x46484A42,
295 .p0_mpwrdlctl
= 0x38383234,
296 .p1_mpwrdlctl
= 0x3C34362E,
300 static struct mx6_ddr_sysinfo mem_dl
= {
303 /* config for full 4GB range so that get_mem_size() works */
316 /* DDR 32bit 512MB */
317 static struct mx6_ddr_sysinfo mem_s
= {
320 /* config for full 4GB range so that get_mem_size() works */
333 static void ccgr_init(void)
335 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
337 writel(0x00003F3F, &ccm
->CCGR0
);
338 writel(0x0030FC00, &ccm
->CCGR1
);
339 writel(0x000FC000, &ccm
->CCGR2
);
340 writel(0x3F300000, &ccm
->CCGR3
);
341 writel(0xFF00F300, &ccm
->CCGR4
);
342 writel(0x0F0000C3, &ccm
->CCGR5
);
343 writel(0x000003CC, &ccm
->CCGR6
);
346 static void gpr_init(void)
348 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
350 /* enable AXI cache for VDOA/VPU/IPU */
351 writel(0xF00000CF, &iomux
->gpr
[4]);
352 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
353 writel(0x007F007F, &iomux
->gpr
[6]);
354 writel(0x007F007F, &iomux
->gpr
[7]);
357 static void spl_dram_init(void)
360 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
361 mx6_dram_cfg(&mem_s
, &mx6dl_mmdc_calib
, &mt41j256
);
362 } else if (is_mx6dl()) {
363 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
364 mx6_dram_cfg(&mem_dl
, &mx6dl_mmdc_calib
, &mt41j256
);
365 } else if (is_mx6dq()) {
366 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs
, &mx6dq_grp_ioregs
);
367 mx6_dram_cfg(&mem_q
, &mx6dq_mmdc_calib
, &mt41j256
);
373 void board_init_f(ulong dummy
)
377 /* setup AIPS and disable watchdog */
383 board_early_init_f();
388 /* UART clocks enabled and gd valid - init serial console */
389 preloader_console_init();
391 /* DDR initialization */
395 memset(__bss_start
, 0, __bss_end
- __bss_start
);
397 /* load/boot image from boot device */
398 board_init_r(NULL
, 0);