2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <fsl_esdhc.h>
17 #include <linux/sizes.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/crm_regs.h>
21 #include <asm/arch/iomux.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/imx-common/iomux-v3.h>
26 DECLARE_GLOBAL_DATA_PTR
;
28 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
29 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
30 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
32 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
33 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
34 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
37 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
38 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
40 static iomux_v3_cfg_t
const uart4_pads
[] = {
41 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
42 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA
| MUX_PAD_CTRL(UART_PAD_CTRL
)),
45 static iomux_v3_cfg_t
const enet_pads
[] = {
46 IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
47 IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK
| MUX_PAD_CTRL(ENET_PAD_CTRL
| PAD_CTL_SRE_FAST
)),
48 IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
49 IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
50 IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
51 IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
52 IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
53 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
54 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
)),
55 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12
| MUX_PAD_CTRL(NO_PAD_CTRL
)),
58 static iomux_v3_cfg_t
const usdhc1_pads
[] = {
59 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
60 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
61 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
62 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
63 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
64 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
)),
65 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01
| MUX_PAD_CTRL(NO_PAD_CTRL
)),/* CD */
68 #ifdef CONFIG_FSL_ESDHC
69 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
71 struct fsl_esdhc_cfg usdhc_cfg
[1] = {
72 {USDHC1_BASE_ADDR
, 0, 4},
75 int board_mmc_getcd(struct mmc
*mmc
)
77 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
80 switch (cfg
->esdhc_base
) {
81 case USDHC1_BASE_ADDR
:
82 ret
= !gpio_get_value(USDHC1_CD_GPIO
);
89 int board_mmc_init(bd_t
*bis
)
94 * According to the board_mmc_init() the following map is done:
95 * (U-boot device node) (Physical Port)
98 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
101 SETUP_IOMUX_PADS(usdhc1_pads
);
102 gpio_direction_input(USDHC1_CD_GPIO
);
103 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
106 printf("Warning - USDHC%d controller not supporting\n",
111 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
113 printf("Warning: failed to initialize mmc dev %d\n", i
);
122 #ifdef CONFIG_FEC_MXC
123 #define ENET_PHY_RST IMX_GPIO_NR(7, 12)
124 static int setup_fec(void)
126 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
127 struct anatop_regs
*anatop
= (struct anatop_regs
*)ANATOP_BASE_ADDR
;
128 s32 timeout
= 100000;
132 /* Enable fec clock */
133 setbits_le32(&ccm
->CCGR1
, MXC_CCM_CCGR1_ENET_MASK
);
136 ret
= enable_fec_anatop_clock(0, ENET_50MHZ
);
141 reg
= readl(&anatop
->pll_enet
);
142 reg
&= ~BM_ANADIG_PLL_SYS_POWERDOWN
;
143 writel(reg
, &anatop
->pll_enet
);
144 reg
= readl(&anatop
->pll_enet
);
145 reg
|= BM_ANADIG_PLL_SYS_ENABLE
;
147 if (readl(&anatop
->pll_enet
) & BM_ANADIG_PLL_SYS_LOCK
)
152 reg
&= ~BM_ANADIG_PLL_SYS_BYPASS
;
153 writel(reg
, &anatop
->pll_enet
);
156 gpio_direction_output(ENET_PHY_RST
, 0);
158 gpio_set_value(ENET_PHY_RST
, 1);
163 int board_eth_init(bd_t
*bis
)
167 SETUP_IOMUX_PADS(enet_pads
);
170 return ret
= cpu_eth_init(bis
);
174 int board_early_init_f(void)
176 SETUP_IOMUX_PADS(uart4_pads
);
183 /* Address of boot parameters */
184 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
191 gd
->ram_size
= imx_ddr_size();
196 #ifdef CONFIG_SPL_BUILD
200 #include <asm/arch/crm_regs.h>
201 #include <asm/arch/mx6-ddr.h>
209 #define IMX6DQ_DRIVE_STRENGTH 0x30
210 #define IMX6SDL_DRIVE_STRENGTH 0x28
212 /* configure MX6Q/DUAL mmdc DDR io registers */
213 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs
= {
232 .dram_sdclk_0
= 0x30,
233 .dram_sdclk_1
= 0x30,
235 .dram_sdcke0
= 0x3000,
236 .dram_sdcke1
= 0x3000,
237 .dram_sdba2
= 0x00000000,
242 /* configure MX6Q/DUAL mmdc GRP io registers */
243 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs
= {
253 .grp_ddrmode_ctl
= 0x00020000,
254 .grp_ddrpke
= 0x00000000,
255 .grp_ddrmode
= 0x00020000,
257 .grp_ddr_type
= 0x000c0000,
260 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
261 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs
= {
262 .dram_sdclk_0
= 0x30,
263 .dram_sdclk_1
= 0x30,
269 .dram_sdba2
= 0x00000000,
290 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
291 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
292 .grp_ddr_type
= 0x000c0000,
293 .grp_ddrmode_ctl
= 0x00020000,
294 .grp_ddrpke
= 0x00000000,
297 .grp_ddrmode
= 0x00020000,
309 static struct mx6_ddr3_cfg mt41j256
= {
323 static struct mx6_mmdc_calibration mx6dq_mmdc_calib
= {
324 .p0_mpwldectrl0
= 0x000E0009,
325 .p0_mpwldectrl1
= 0x0018000E,
326 .p1_mpwldectrl0
= 0x00000007,
327 .p1_mpwldectrl1
= 0x00000000,
328 .p0_mpdgctrl0
= 0x43280334,
329 .p0_mpdgctrl1
= 0x031C0314,
330 .p1_mpdgctrl0
= 0x4318031C,
331 .p1_mpdgctrl1
= 0x030C0258,
332 .p0_mprddlctl
= 0x3E343A40,
333 .p1_mprddlctl
= 0x383C3844,
334 .p0_mpwrdlctl
= 0x40404440,
335 .p1_mpwrdlctl
= 0x4C3E4446,
339 static struct mx6_ddr_sysinfo mem_q
= {
340 .ddr_type
= DDR_TYPE_DDR3
,
343 /* config for full 4GB range so that get_mem_size() works */
356 static struct mx6_mmdc_calibration mx6dl_mmdc_calib
= {
357 .p0_mpwldectrl0
= 0x001F0024,
358 .p0_mpwldectrl1
= 0x00110018,
359 .p1_mpwldectrl0
= 0x001F0024,
360 .p1_mpwldectrl1
= 0x00110018,
361 .p0_mpdgctrl0
= 0x4230022C,
362 .p0_mpdgctrl1
= 0x02180220,
363 .p1_mpdgctrl0
= 0x42440248,
364 .p1_mpdgctrl1
= 0x02300238,
365 .p0_mprddlctl
= 0x44444A48,
366 .p1_mprddlctl
= 0x46484A42,
367 .p0_mpwrdlctl
= 0x38383234,
368 .p1_mpwrdlctl
= 0x3C34362E,
372 static struct mx6_ddr_sysinfo mem_dl
= {
375 /* config for full 4GB range so that get_mem_size() works */
388 /* DDR 32bit 512MB */
389 static struct mx6_ddr_sysinfo mem_s
= {
392 /* config for full 4GB range so that get_mem_size() works */
405 static void ccgr_init(void)
407 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
409 writel(0x00003F3F, &ccm
->CCGR0
);
410 writel(0x0030FC00, &ccm
->CCGR1
);
411 writel(0x000FC000, &ccm
->CCGR2
);
412 writel(0x3F300000, &ccm
->CCGR3
);
413 writel(0xFF00F300, &ccm
->CCGR4
);
414 writel(0x0F0000C3, &ccm
->CCGR5
);
415 writel(0x000003CC, &ccm
->CCGR6
);
418 static void gpr_init(void)
420 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
422 /* enable AXI cache for VDOA/VPU/IPU */
423 writel(0xF00000CF, &iomux
->gpr
[4]);
424 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
425 writel(0x007F007F, &iomux
->gpr
[6]);
426 writel(0x007F007F, &iomux
->gpr
[7]);
429 static void spl_dram_init(void)
432 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
433 mx6_dram_cfg(&mem_s
, &mx6dl_mmdc_calib
, &mt41j256
);
434 } else if (is_mx6dl()) {
435 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs
, &mx6sdl_grp_ioregs
);
436 mx6_dram_cfg(&mem_dl
, &mx6dl_mmdc_calib
, &mt41j256
);
437 } else if (is_mx6dq()) {
438 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs
, &mx6dq_grp_ioregs
);
439 mx6_dram_cfg(&mem_q
, &mx6dq_mmdc_calib
, &mt41j256
);
445 void board_init_f(ulong dummy
)
449 /* setup AIPS and disable watchdog */
455 board_early_init_f();
460 /* UART clocks enabled and gd valid - init serial console */
461 preloader_console_init();
463 /* DDR initialization */
467 memset(__bss_start
, 0, __bss_end
- __bss_start
);
469 /* load/boot image from boot device */
470 board_init_r(NULL
, 0);